From dedd6c9534c55a09048aa15bffb3e9de2253badd Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 6 Nov 2019 20:46:06 +0100 Subject: Add testcase for #1005 --- testsuite/synth/issue1005/test.vhdl | 22 ++++++++++++++++++++++ testsuite/synth/issue1005/testsuite.sh | 12 ++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 testsuite/synth/issue1005/test.vhdl create mode 100755 testsuite/synth/issue1005/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/synth/issue1005/test.vhdl b/testsuite/synth/issue1005/test.vhdl new file mode 100644 index 000000000..0388e33f4 --- /dev/null +++ b/testsuite/synth/issue1005/test.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.env.stop; + +entity test is + generic ( + SIM : boolean := false + ); + port ( + val : in std_ulogic + ); +end entity test; + +architecture behaviour of test is +begin + process_0: process(all) + begin + if SIM and val = '1' then + stop; + end if; + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue1005/testsuite.sh b/testsuite/synth/issue1005/testsuite.sh new file mode 100755 index 000000000..5643f943a --- /dev/null +++ b/testsuite/synth/issue1005/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +t=test +synth $t.vhdl -e $t > syn_$t.vhdl +analyze syn_$t.vhdl + +clean + +echo "Test successful" -- cgit v1.2.3