From db69b8f4bb4a27971774aa8ac2a93e10383a4b83 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 15 Apr 2021 07:24:37 +0200
Subject: testsuite/gna: add test for #1724

---
 testsuite/gna/issue1724/const_test.vhdl       | 16 ++++++++++++++++
 testsuite/gna/issue1724/const_test_vunit.vhdl |  8 ++++++++
 testsuite/gna/issue1724/testsuite.sh          |  9 +++++++++
 3 files changed, 33 insertions(+)
 create mode 100644 testsuite/gna/issue1724/const_test.vhdl
 create mode 100644 testsuite/gna/issue1724/const_test_vunit.vhdl
 create mode 100755 testsuite/gna/issue1724/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue1724/const_test.vhdl b/testsuite/gna/issue1724/const_test.vhdl
new file mode 100644
index 000000000..0a18e5b01
--- /dev/null
+++ b/testsuite/gna/issue1724/const_test.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity const_test is
+    generic (
+        addr_width : positive := 5
+    );
+    port (
+        clk : in std_logic
+    );
+end entity;
+
+architecture rtl of const_test is
+begin
+end architecture rtl;
diff --git a/testsuite/gna/issue1724/const_test_vunit.vhdl b/testsuite/gna/issue1724/const_test_vunit.vhdl
new file mode 100644
index 000000000..715049120
--- /dev/null
+++ b/testsuite/gna/issue1724/const_test_vunit.vhdl
@@ -0,0 +1,8 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+vunit const_test_vunit (const_test(rtl))
+{
+    constant depth : positive := 2**addr_width;
+}
diff --git a/testsuite/gna/issue1724/testsuite.sh b/testsuite/gna/issue1724/testsuite.sh
new file mode 100755
index 000000000..8da89781d
--- /dev/null
+++ b/testsuite/gna/issue1724/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+$GHDL -s --std=08 const_test.vhdl const_test_vunit.vhdl
+
+clean
+
+echo "Test successful"
-- 
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