From d2ea6d49cd301ff7bd129bfe39a09b0b14f4dbcc Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 29 Apr 2022 12:01:37 +0200
Subject: testsuite/synth: add new tests for attributes

---
 testsuite/synth/attr01/attr01.vhdl  | 31 +++++++++++++++++++++++++++++++
 testsuite/synth/attr01/attr02.vhdl  | 31 +++++++++++++++++++++++++++++++
 testsuite/synth/attr01/testsuite.sh | 14 ++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 testsuite/synth/attr01/attr01.vhdl
 create mode 100644 testsuite/synth/attr01/attr02.vhdl
 create mode 100755 testsuite/synth/attr01/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/attr01/attr01.vhdl b/testsuite/synth/attr01/attr01.vhdl
new file mode 100644
index 000000000..1211efa24
--- /dev/null
+++ b/testsuite/synth/attr01/attr01.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity attr01 is
+  port (
+    rst : std_logic;
+    clk : std_logic;
+    cnt : out std_logic_vector (7 downto 0)
+    );
+end attr01;
+
+architecture behav of attr01 is
+  signal counter : std_logic_vector (7 downto 0);
+
+  attribute keep : boolean;
+  attribute keep of counter : signal is True;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst = '1' then
+        counter <= (others => '0');
+      else
+        counter <= std_logic_vector (unsigned (counter) + 1);
+      end if;
+    end if;
+  end process;
+
+  cnt <= counter;
+end behav;
diff --git a/testsuite/synth/attr01/attr02.vhdl b/testsuite/synth/attr01/attr02.vhdl
new file mode 100644
index 000000000..bb7016bde
--- /dev/null
+++ b/testsuite/synth/attr01/attr02.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity attr02 is
+  port (
+    rst : std_logic;
+    clk : std_logic;
+    cnt : out std_logic_vector (7 downto 0)
+    );
+  attribute keep : boolean;
+  attribute keep of rst : signal is True;
+end attr02;
+
+architecture behav of attr02 is
+  signal counter : std_logic_vector (7 downto 0);
+
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      if rst = '1' then
+        counter <= (others => '0');
+      else
+        counter <= std_logic_vector (unsigned (counter) + 1);
+      end if;
+    end if;
+  end process;
+
+  cnt <= counter;
+end behav;
diff --git a/testsuite/synth/attr01/testsuite.sh b/testsuite/synth/attr01/testsuite.sh
new file mode 100755
index 000000000..8fd0c9051
--- /dev/null
+++ b/testsuite/synth/attr01/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_analyze attr01
+grep -q "keep of counter" syn_attr01.vhdl
+clean
+
+synth_analyze attr02
+grep -q "keep of rst" syn_attr02.vhdl
+clean
+
+echo "Test successful"
-- 
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