From c5e5eaf8e039f615ea26f4ff4460ba12de633a21 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 16 Feb 2016 20:56:12 +0100
Subject: Add testcase for isse43.

---
 testsuite/gna/issue43/repro.vhdl   | 28 ++++++++++++++++++
 testsuite/gna/issue43/repro2.vhdl  | 23 +++++++++++++++
 testsuite/gna/issue43/run.py       | 14 +++++++++
 testsuite/gna/issue43/test_tb.vhd  | 60 ++++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue43/testsuite.sh | 10 +++++++
 5 files changed, 135 insertions(+)
 create mode 100644 testsuite/gna/issue43/repro.vhdl
 create mode 100644 testsuite/gna/issue43/repro2.vhdl
 create mode 100644 testsuite/gna/issue43/run.py
 create mode 100644 testsuite/gna/issue43/test_tb.vhd
 create mode 100755 testsuite/gna/issue43/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue43/repro.vhdl b/testsuite/gna/issue43/repro.vhdl
new file mode 100644
index 000000000..883b2be27
--- /dev/null
+++ b/testsuite/gna/issue43/repro.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_tb is
+end entity;
+
+architecture beh of test_tb is
+  signal rx_data : std_logic_vector(159 downto 0);
+  
+  procedure to_t( signal sa : out std_logic_vector(31 downto 0))  is
+  begin
+    sa <= (others => '1');
+	assert false report "lol";
+  end procedure;
+begin
+
+  asd : for i in 0 to 4 generate
+  begin
+    process
+    begin
+--      rx_data(32*(i+1)-1 downto 32*i) <= (others => '0');
+      wait for 10 ns;
+      to_t(rx_data(32*(i+1)-1 downto 32*i));
+      wait;
+    end process;
+  end generate;
+  
+end architecture;
diff --git a/testsuite/gna/issue43/repro2.vhdl b/testsuite/gna/issue43/repro2.vhdl
new file mode 100644
index 000000000..71d9d4c11
--- /dev/null
+++ b/testsuite/gna/issue43/repro2.vhdl
@@ -0,0 +1,23 @@
+entity test_tb is
+end entity;
+
+architecture beh of test_tb is
+  signal rx_data : bit_vector(159 downto 0);
+  
+  procedure to_t( signal sa : out bit_vector(31 downto 0))  is
+  begin
+    sa <= (others => '1');
+	assert false report "lol";
+  end procedure;
+begin
+  asd : for i in 0 to 4 generate
+  begin
+    process
+    begin
+      wait for 10 ns;
+      to_t(rx_data(32*(i+1)-1 downto 32*i));
+      wait;
+    end process;
+  end generate;
+  
+end architecture;
diff --git a/testsuite/gna/issue43/run.py b/testsuite/gna/issue43/run.py
new file mode 100644
index 000000000..f1cb5ec01
--- /dev/null
+++ b/testsuite/gna/issue43/run.py
@@ -0,0 +1,14 @@
+import os
+import sys
+from string import join
+from vunit import VUnit
+
+
+
+# Create VUnit instance by parsing command line arguments
+vu = VUnit.from_argv()
+vu.add_com()
+lib = vu.add_library("lib")
+lib.add_source_files("*.vhd")
+
+vu.main()
\ No newline at end of file
diff --git a/testsuite/gna/issue43/test_tb.vhd b/testsuite/gna/issue43/test_tb.vhd
new file mode 100644
index 000000000..a4d8be554
--- /dev/null
+++ b/testsuite/gna/issue43/test_tb.vhd
@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library vunit_lib;
+context vunit_lib.vunit_context;
+context vunit_lib.com_context;
+
+entity test_tb is
+generic (runner_cfg : runner_cfg_t);
+
+end entity;
+
+architecture beh of test_tb is
+  signal rx_data : std_logic_vector(159 downto 0);
+  
+  function to_b(constant s : string) return std_logic is
+  begin
+	return '0';
+  end function;
+  
+  function to_a(constant s : string) return std_logic is
+    variable a : std_logic := to_b(s);
+  begin
+	return '0';
+  end function;
+  
+  procedure to_t( signal sa : out std_logic_vector(31 downto 0))  is
+  begin
+    sa <= (others => '1');
+	assert false report "lol";
+  end procedure;
+begin
+	
+  asd : for i in 0 to 4 generate
+  begin
+	process
+		constant s : string := "lane" & integer'image(i);
+		variable self : actor_t := create(s);
+	begin
+		--assert false report "Error: " & s;
+		
+		rx_data(32*(i+1)-1 downto 32*i) <= (others => '0');
+		wait for 10 ns;
+		to_t(rx_data(32*(i+1)-1 downto 32*i));
+		wait;
+	end process;
+  end generate;
+  
+  process
+  begin
+	test_runner_setup(runner, runner_cfg);
+    while test_suite loop
+		if run("test1") then
+		null;
+		end if;
+	end loop;
+    test_runner_cleanup(runner); -- Simulation ends here
+  end process;
+
+end architecture;
\ No newline at end of file
diff --git a/testsuite/gna/issue43/testsuite.sh b/testsuite/gna/issue43/testsuite.sh
new file mode 100755
index 000000000..fabbce8b6
--- /dev/null
+++ b/testsuite/gna/issue43/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze repro2.vhdl
+elab_simulate test_tb
+
+clean test
+
+echo "Test successful"
-- 
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