From c26973e620349e8ceb87b22c89c92ae82b8a75f9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 30 Sep 2021 06:47:16 +0200
Subject: testsuite/gna: add a test for #1759

---
 testsuite/gna/issue1759/repro.vhdl   | 18 ++++++++++++++++++
 testsuite/gna/issue1759/testsuite.sh | 20 ++++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 testsuite/gna/issue1759/repro.vhdl
 create mode 100755 testsuite/gna/issue1759/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue1759/repro.vhdl b/testsuite/gna/issue1759/repro.vhdl
new file mode 100644
index 000000000..a4a932531
--- /dev/null
+++ b/testsuite/gna/issue1759/repro.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+end;
+
+architecture behav of repro is
+  signal s : std_logic := '0';
+begin
+  process
+  begin
+    for v in std_logic loop
+      s <= v;
+      wait for 1 ns;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue1759/testsuite.sh b/testsuite/gna/issue1759/testsuite.sh
new file mode 100755
index 000000000..bf1a421e0
--- /dev/null
+++ b/testsuite/gna/issue1759/testsuite.sh
@@ -0,0 +1,20 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze repro.vhdl
+elab repro
+if ghdl_has_feature repro vcd; then
+  simulate repro --vcd=repro-std.vcd
+  simulate repro --vcd=repro-vlg.vcd --vcd-4states
+
+  if fgrep -q "U!" repro-vlg.vcd; then
+    echo "error: non-verilog state in vcd"
+    exit 1;
+  fi
+fi
+
+clean
+rm -f repro-*.vcd
+
+echo "Test successful"
-- 
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