From bc269c6a47da7aaefb0bfb85cea3ad08447ab1b0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 11 Apr 2020 15:37:27 +0200
Subject: testsuite/synth: add a test for #1210

---
 testsuite/synth/issue1210/bug.vhdl     | 15 +++++++++++++++
 testsuite/synth/issue1210/testsuite.sh |  7 +++++++
 2 files changed, 22 insertions(+)
 create mode 100644 testsuite/synth/issue1210/bug.vhdl
 create mode 100755 testsuite/synth/issue1210/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue1210/bug.vhdl b/testsuite/synth/issue1210/bug.vhdl
new file mode 100644
index 000000000..2bd385609
--- /dev/null
+++ b/testsuite/synth/issue1210/bug.vhdl
@@ -0,0 +1,15 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.math_real.all;
+
+entity bug is
+  port (
+    dummy   : in std_ulogic
+  );
+end entity;
+
+architecture rtl of bug is
+	constant a : real := floor(15.0/4.0);
+	constant b : real := ceil(15.0/4.0);
+begin
+end architecture;
diff --git a/testsuite/synth/issue1210/testsuite.sh b/testsuite/synth/issue1210/testsuite.sh
new file mode 100755
index 000000000..6f3c0d0e6
--- /dev/null
+++ b/testsuite/synth/issue1210/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth bug.vhdl -e > syn_bug.vhdl
+
+echo "Test successful"
-- 
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