From bb5e89e7f96669c94f2816599c56390a23b123d2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 11 Nov 2021 05:06:51 +0100
Subject: testsuite/synth: add a test for #1909

---
 testsuite/synth/issue1909/reproducebug.vhdl    | 27 ++++++++++++++++++++++
 testsuite/synth/issue1909/tb_reproducebug.vhdl | 31 ++++++++++++++++++++++++++
 testsuite/synth/issue1909/testsuite.sh         |  9 ++++++++
 3 files changed, 67 insertions(+)
 create mode 100644 testsuite/synth/issue1909/reproducebug.vhdl
 create mode 100644 testsuite/synth/issue1909/tb_reproducebug.vhdl
 create mode 100755 testsuite/synth/issue1909/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue1909/reproducebug.vhdl b/testsuite/synth/issue1909/reproducebug.vhdl
new file mode 100644
index 000000000..60655b0eb
--- /dev/null
+++ b/testsuite/synth/issue1909/reproducebug.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity ReproduceBug is
+  port(
+    clk      : in std_logic;
+    input    : in unsigned(7 downto 0);
+    output   : out unsigned(7 downto 0)
+  );
+end ReproduceBug;
+
+architecture rtl of ReproduceBug is
+  -- only to get rid of "latch inferrence" warning
+ -- signal outputLcl : unsigned(7 downto 0) := (others => '0'); 
+begin
+
+  Main: process(clk)
+  begin
+    if rising_edge(Clk) then
+      output <= input ror 1; -- can also be 'rol'
+    end if;
+  end process;
+
+--  output <= outputLcl; 
+
+end rtl;
diff --git a/testsuite/synth/issue1909/tb_reproducebug.vhdl b/testsuite/synth/issue1909/tb_reproducebug.vhdl
new file mode 100644
index 000000000..8ebbcdc4a
--- /dev/null
+++ b/testsuite/synth/issue1909/tb_reproducebug.vhdl
@@ -0,0 +1,31 @@
+entity tb_reproducebug is
+end tb_reproducebug;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_reproducebug is
+  signal clk      : std_logic;
+  signal input    : unsigned(7 downto 0);
+  signal output   : unsigned(7 downto 0);
+begin
+  dut: entity work.reproducebug
+    port map (clk, input, output);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end;
+  begin
+    input <= x"14";
+    pulse;
+    assert output = x"0a" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1909/testsuite.sh b/testsuite/synth/issue1909/testsuite.sh
new file mode 100755
index 000000000..89e0ae98a
--- /dev/null
+++ b/testsuite/synth/issue1909/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in reproducebug; do
+    synth_tb $t
+done
+
+echo "Test successful"
-- 
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