From b46d4db8b112d40b056c102d65a64d08a00f4668 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 7 Aug 2020 21:49:31 +0200 Subject: testsuite/synth: add more tests for std_logic_arith --- testsuite/synth/sns01/exts.vhdl | 19 ++++++++ testsuite/synth/sns01/muls.vhdl | 34 ++++++++++++++ testsuite/synth/sns01/shrs.vhdl | 24 ++++++++++ testsuite/synth/sns01/tb_exts.vhdl | 47 ++++++++++++++++++++ testsuite/synth/sns01/tb_muls.vhdl | 84 +++++++++++++++++++++++++++++++++++ testsuite/synth/sns01/tb_shrs.vhdl | 64 ++++++++++++++++++++++++++ testsuite/synth/sns01/tb_unaries.vhdl | 65 +++++++++++++++++++++++++++ testsuite/synth/sns01/testsuite.sh | 2 +- testsuite/synth/sns01/unaries.vhdl | 33 ++++++++++++++ 9 files changed, 371 insertions(+), 1 deletion(-) create mode 100644 testsuite/synth/sns01/exts.vhdl create mode 100644 testsuite/synth/sns01/muls.vhdl create mode 100644 testsuite/synth/sns01/shrs.vhdl create mode 100644 testsuite/synth/sns01/tb_exts.vhdl create mode 100644 testsuite/synth/sns01/tb_muls.vhdl create mode 100644 testsuite/synth/sns01/tb_shrs.vhdl create mode 100644 testsuite/synth/sns01/tb_unaries.vhdl create mode 100644 testsuite/synth/sns01/unaries.vhdl (limited to 'testsuite') diff --git a/testsuite/synth/sns01/exts.vhdl b/testsuite/synth/sns01/exts.vhdl new file mode 100644 index 000000000..e7a82730a --- /dev/null +++ b/testsuite/synth/sns01/exts.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity exts is + port ( + l3 : std_logic_vector (2 downto 0); + + ext_u3 : out std_logic_vector (4 downto 0); + sxt_s3 : out std_logic_vector (4 downto 0)); +end exts; + +library ieee; +use ieee.std_logic_arith.all; + +architecture behav of exts is +begin + ext_u3 <= ext(l3, 5); + sxt_s3 <= sxt(l3, 5); +end behav; diff --git a/testsuite/synth/sns01/muls.vhdl b/testsuite/synth/sns01/muls.vhdl new file mode 100644 index 000000000..01e5a9c84 --- /dev/null +++ b/testsuite/synth/sns01/muls.vhdl @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity muls is + port ( + l4 : std_logic_vector (3 downto 0); + r3 : std_logic_vector (2 downto 0); + + mul_u4u3u : out std_logic_vector (6 downto 0); + mul_s4s3s : out std_logic_vector (6 downto 0); + mul_u4s3s : out std_logic_vector (7 downto 0); + mul_s4u3s : out std_logic_vector (7 downto 0); + + mul_u4u3v : out std_logic_vector (6 downto 0); + mul_s4s3v : out std_logic_vector (6 downto 0); + mul_u4s3v : out std_logic_vector (7 downto 0); + mul_s4u3v : out std_logic_vector (7 downto 0)); +end muls; + +library ieee; +use ieee.std_logic_arith.all; + +architecture behav of muls is +begin + mul_u4u3u <= std_logic_vector (unsigned'(unsigned(l4) * unsigned(r3))); + mul_s4s3s <= std_logic_vector (signed'(signed(l4) * signed(r3))); + mul_u4s3s <= std_logic_vector (signed'(unsigned(l4) * signed(r3))); + mul_s4u3s <= std_logic_vector (signed'(signed(l4) * unsigned(r3))); + + mul_u4u3v <= unsigned(l4) * unsigned(r3); + mul_s4s3v <= signed(l4) * signed(r3); + mul_u4s3v <= unsigned(l4) * signed(r3); + mul_s4u3v <= signed(l4) * unsigned(r3); +end behav; diff --git a/testsuite/synth/sns01/shrs.vhdl b/testsuite/synth/sns01/shrs.vhdl new file mode 100644 index 000000000..9a8cc6e14 --- /dev/null +++ b/testsuite/synth/sns01/shrs.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity shrs is + port ( + l3 : std_logic_vector (2 downto 0); + r4 : std_logic_vector (3 downto 0); + + shl_u3u4u : out std_logic_vector (2 downto 0); + shl_s3u4s : out std_logic_vector (2 downto 0); + shr_u3u4u : out std_logic_vector (2 downto 0); + shr_s3u4s : out std_logic_vector (2 downto 0)); +end shrs; + +library ieee; +use ieee.std_logic_arith.all; + +architecture behav of shrs is +begin + shl_u3u4u <= std_logic_vector (shl(unsigned(l3), unsigned(r4))); + shl_s3u4s <= std_logic_vector (shl(signed(l3), unsigned(r4))); + shr_u3u4u <= std_logic_vector (shr(unsigned(l3), unsigned(r4))); + shr_s3u4s <= std_logic_vector (shr(signed(l3), unsigned(r4))); +end behav; diff --git a/testsuite/synth/sns01/tb_exts.vhdl b/testsuite/synth/sns01/tb_exts.vhdl new file mode 100644 index 000000000..09887c58f --- /dev/null +++ b/testsuite/synth/sns01/tb_exts.vhdl @@ -0,0 +1,47 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity tb_exts is +end; + +architecture behav of tb_exts is + type sl_map_type is array (std_ulogic) of character; + constant sl_map : sl_map_type := "UX01ZWLH-"; + + function to_string(v : std_logic_vector) return string + is + alias av : std_logic_vector(1 to v'length) is v; + variable res : string (1 to v'length); + begin + for i in res'range loop + res (i) := sl_map (av (i)); + end loop; + return res; + end to_string; + + signal li : integer := 0; + + signal l3 : std_logic_vector (2 downto 0) := "000"; + signal ext_u3 : std_logic_vector (4 downto 0); + signal sxt_s3 : std_logic_vector (4 downto 0); +begin + + dut: entity work.exts + port map ( + l3 => l3, + ext_u3 => ext_u3, + sxt_s3 => sxt_s3); + + process + begin + for i in -4 to 3 loop + li <= i; + l3 <= conv_std_logic_vector (i, 3); + wait for 1 ns; + report "u3: ext " & integer'image(i) & " = " & to_string(ext_u3); + report "s3: sxt " & integer'image(i) & " = " & to_string(sxt_s3); + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/sns01/tb_muls.vhdl b/testsuite/synth/sns01/tb_muls.vhdl new file mode 100644 index 000000000..47c8e79a1 --- /dev/null +++ b/testsuite/synth/sns01/tb_muls.vhdl @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity tb_muls is +end; + +architecture behav of tb_muls is + type sl_map_type is array (std_ulogic) of character; + constant sl_map : sl_map_type := "UX01ZWLH-"; + + function to_string(v : std_logic_vector) return string + is + alias av : std_logic_vector(1 to v'length) is v; + variable res : string (1 to v'length); + begin + for i in res'range loop + res (i) := sl_map (av (i)); + end loop; + return res; + end to_string; + + signal li : integer := 0; + signal ri : integer := 0; + signal l4 : std_logic_vector (3 downto 0) := "0000"; + signal r3 : std_logic_vector (2 downto 0) := "000"; + signal mul_u4u3u : std_logic_vector (6 downto 0); + signal mul_s4s3s : std_logic_vector (6 downto 0); + signal mul_u4s3s : std_logic_vector (7 downto 0); + signal mul_s4u3s : std_logic_vector (7 downto 0); + + signal mul_u4u3v : std_logic_vector (6 downto 0); + signal mul_s4s3v : std_logic_vector (6 downto 0); + signal mul_u4s3v : std_logic_vector (7 downto 0); + signal mul_s4u3v : std_logic_vector (7 downto 0); +begin + + dut: entity work.muls + port map ( + l4 => l4, + r3 => r3, + mul_u4u3u => mul_u4u3u, + mul_s4s3s => mul_s4s3s, + mul_u4s3s => mul_u4s3s, + mul_s4u3s => mul_s4u3s, + + mul_u4u3v => mul_u4u3v, + mul_s4s3v => mul_s4s3v, + mul_u4s3v => mul_u4s3v, + mul_s4u3v => mul_s4u3v); + + process + begin + for i in -8 to 7 loop + li <= i; + l4 <= conv_std_logic_vector (i, 4); + for j in -4 to 3 loop + r3 <= conv_std_logic_vector (j, 3); + ri <= j; + wait for 1 ns; + report "u4u3u: " & integer'image(i) & " * " & integer'image(j) & " = " + & to_string(mul_u4u3u); + report "s4s3s: " & integer'image(i) & " * " & integer'image(j) & " = " + & to_string(mul_s4s3s); + report "u4s3s: " & integer'image(i) & " * " & integer'image(j) & " = " + & to_string(mul_u4s3s); + report "s4u3s: " & integer'image(i) & " * " & integer'image(j) & " = " + & to_string(mul_s4u3s); + + ------ + + report "u4u3v: " & integer'image(i) & " * " & integer'image(j) & " = " + & to_string(mul_u4u3v); + report "s4s3v: " & integer'image(i) & " * " & integer'image(j) & " = " + & to_string(mul_s4s3v); + report "u4s3v: " & integer'image(i) & " * " & integer'image(j) & " = " + & to_string(mul_u4s3v); + report "s4u3v: " & integer'image(i) & " * " & integer'image(j) & " = " + & to_string(mul_s4u3v); + end loop; + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/sns01/tb_shrs.vhdl b/testsuite/synth/sns01/tb_shrs.vhdl new file mode 100644 index 000000000..1901ec3f2 --- /dev/null +++ b/testsuite/synth/sns01/tb_shrs.vhdl @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity tb_shrs is +end; + +architecture behav of tb_shrs is + type sl_map_type is array (std_ulogic) of character; + constant sl_map : sl_map_type := "UX01ZWLH-"; + + function to_string(v : std_logic_vector) return string + is + alias av : std_logic_vector(1 to v'length) is v; + variable res : string (1 to v'length); + begin + for i in res'range loop + res (i) := sl_map (av (i)); + end loop; + return res; + end to_string; + + signal li : integer := 0; + signal ri : integer := 0; + + signal l3 : std_logic_vector (2 downto 0) := "000"; + signal r4 : std_logic_vector (3 downto 0) := "0000"; + signal shl_u3u4u : std_logic_vector (2 downto 0); + signal shl_s3u4s : std_logic_vector (2 downto 0); + signal shr_u3u4u : std_logic_vector (2 downto 0); + signal shr_s3u4s : std_logic_vector (2 downto 0); +begin + + dut: entity work.shrs + port map ( + l3 => l3, + r4 => r4, + shl_u3u4u => shl_u3u4u, + shl_s3u4s => shl_s3u4s, + shr_u3u4u => shr_u3u4u, + shr_s3u4s => shr_s3u4s); + + process + begin + for i in -4 to 3 loop + li <= i; + l3 <= conv_std_logic_vector (i, 3); + for j in 0 to 5 loop + r4 <= conv_std_logic_vector (j, 4); + ri <= j; + wait for 1 ns; + report "u3u4u: " & integer'image(i) & " shl " & integer'image(j) & " = " + & to_string(shl_u3u4u); + report "s3u4s: " & integer'image(i) & " shl " & integer'image(j) & " = " + & to_string(shl_s3u4s); + report "u3u4u: " & integer'image(i) & " shr " & integer'image(j) & " = " + & to_string(shr_u3u4u); + report "s3u4s: " & integer'image(i) & " shr " & integer'image(j) & " = " + & to_string(shr_s3u4s); + end loop; + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/sns01/tb_unaries.vhdl b/testsuite/synth/sns01/tb_unaries.vhdl new file mode 100644 index 000000000..282ac0355 --- /dev/null +++ b/testsuite/synth/sns01/tb_unaries.vhdl @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity tb_unaries is +end; + +architecture behav of tb_unaries is + type sl_map_type is array (std_ulogic) of character; + constant sl_map : sl_map_type := "UX01ZWLH-"; + + function to_string(v : std_logic_vector) return string + is + alias av : std_logic_vector(1 to v'length) is v; + variable res : string (1 to v'length); + begin + for i in res'range loop + res (i) := sl_map (av (i)); + end loop; + return res; + end to_string; + + signal li : integer; + signal l4 : std_logic_vector (3 downto 0); + signal plus_u4u : std_logic_vector (3 downto 0); + signal plus_s4s : std_logic_vector (3 downto 0); + signal minus_s4s : std_logic_vector (3 downto 0); + signal abs_s4s : std_logic_vector (3 downto 0); + signal plus_u4v : std_logic_vector (3 downto 0); + signal plus_s4v : std_logic_vector (3 downto 0); + signal minus_s4v : std_logic_vector (3 downto 0); + signal abs_s4v : std_logic_vector (3 downto 0); +begin + dut: entity work.unaries + port map ( + l4 => l4, + plus_u4u => plus_u4u, + plus_s4s => plus_s4s, + minus_s4s => minus_s4s, + abs_s4s => abs_s4s, + + plus_u4v => plus_u4v, + plus_s4v => plus_s4v, + minus_s4v => minus_s4v, + abs_s4v => abs_s4v); + + process + begin + for i in -8 to 7 loop + li <= i; + l4 <= conv_std_logic_vector (i, 4); + wait for 1 ns; + report "u4u: + " & integer'image(i) & " = " & to_string(plus_u4u); + report "s4s: + " & integer'image(i) & " = " & to_string(plus_s4s); + report "s4s: - " & integer'image(i) & " = " & to_string(minus_s4s); + report "s4s: abs " & integer'image(i) & " = " & to_string(abs_s4s); + + report "u4v: + " & integer'image(i) & " = " & to_string(plus_u4v); + report "s4v: + " & integer'image(i) & " = " & to_string(plus_s4v); + report "s4v: - " & integer'image(i) & " = " & to_string(minus_s4v); + report "s4v: abs " & integer'image(i) & " = " & to_string(abs_s4v); + end loop; + wait; + end process; +end behav; diff --git a/testsuite/synth/sns01/testsuite.sh b/testsuite/synth/sns01/testsuite.sh index c6f573dd1..4a4ff76cd 100755 --- a/testsuite/synth/sns01/testsuite.sh +++ b/testsuite/synth/sns01/testsuite.sh @@ -5,7 +5,7 @@ GHDL_STD_FLAGS=-fsynopsys # Compare opers. -for f in adds subs cmplt cmple cmpgt cmpge cmpeq cmpne; do +for f in adds subs unaries muls cmplt cmple cmpgt cmpge cmpeq cmpne shrs exts; do analyze $f.vhdl analyze tb_$f.vhdl elab_simulate tb_$f > $f.ref diff --git a/testsuite/synth/sns01/unaries.vhdl b/testsuite/synth/sns01/unaries.vhdl new file mode 100644 index 000000000..3a58f6592 --- /dev/null +++ b/testsuite/synth/sns01/unaries.vhdl @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity unaries is + port ( + l4 : std_logic_vector (3 downto 0); + + plus_u4u : out std_logic_vector (3 downto 0); + plus_s4s : out std_logic_vector (3 downto 0); + minus_s4s : out std_logic_vector (3 downto 0); + abs_s4s : out std_logic_vector (3 downto 0); + + plus_u4v : out std_logic_vector (3 downto 0); + plus_s4v : out std_logic_vector (3 downto 0); + minus_s4v : out std_logic_vector (3 downto 0); + abs_s4v : out std_logic_vector (3 downto 0)); +end unaries; + +library ieee; +use ieee.std_logic_arith.all; + +architecture behav of unaries is +begin + plus_u4u <= std_logic_vector (unsigned'(+unsigned(l4))); + plus_s4s <= std_logic_vector (signed'(+signed(l4))); + minus_s4s <= std_logic_vector (signed'(-signed(l4))); + abs_s4s <= std_logic_vector (signed'(abs signed(l4))); + + plus_u4v <= +unsigned(l4); + plus_s4v <= +signed(l4); + minus_s4v <= -signed(l4); + abs_s4v <= abs signed(l4); +end behav; -- cgit v1.2.3