From a3e05191a62482c385ca5481caa78299fdbad775 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 3 Aug 2022 06:57:25 +0200 Subject: testsuite/gna: add a test for #2157 --- testsuite/gna/issue2157/issue.vhdl | 181 +++++++++++++++++++++++++++++++++++ testsuite/gna/issue2157/repro.vhdl | 20 ++++ testsuite/gna/issue2157/repro2.vhdl | 34 +++++++ testsuite/gna/issue2157/testsuite.sh | 11 +++ testsuite/gna/issue2157/trepro.vhdl | 140 +++++++++++++++++++++++++++ 5 files changed, 386 insertions(+) create mode 100644 testsuite/gna/issue2157/issue.vhdl create mode 100644 testsuite/gna/issue2157/repro.vhdl create mode 100644 testsuite/gna/issue2157/repro2.vhdl create mode 100755 testsuite/gna/issue2157/testsuite.sh create mode 100644 testsuite/gna/issue2157/trepro.vhdl (limited to 'testsuite') diff --git a/testsuite/gna/issue2157/issue.vhdl b/testsuite/gna/issue2157/issue.vhdl new file mode 100644 index 000000000..4545c06b0 --- /dev/null +++ b/testsuite/gna/issue2157/issue.vhdl @@ -0,0 +1,181 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity sequencer is + generic ( + seq : string + ); + port ( + clk : in std_logic; + data : out std_logic + ); +end entity sequencer; + +architecture rtl of sequencer is + + signal index : natural := seq'low; + + function to_bit (a : in character) return std_logic is + variable ret : std_logic; + begin + case a is + when '0' | '_' => ret := '0'; + when '1' | '-' => ret := '1'; + when others => ret := 'X'; + end case; + return ret; + end function to_bit; + +begin + + process (clk) is + begin + if rising_edge(clk) then + if (index < seq'high) then + index <= index + 1; + end if; + end if; + end process; + + data <= to_bit(seq(index)); + +end architecture rtl; + +library ieee; + use ieee.std_logic_1164.all; + +entity hex_sequencer is + generic ( + seq : string + ); + port ( + clk : in std_logic; + data : out std_logic_vector(3 downto 0) + ); +end entity hex_sequencer; + +architecture rtl of hex_sequencer is + + signal index : natural := seq'low; + + function to_hex (a : in character) return std_logic_vector is + variable ret : std_logic_vector(3 downto 0); + begin + case a is + when '0' | '_' => ret := x"0"; + when '1' => ret := x"1"; + when '2' => ret := x"2"; + when '3' => ret := x"3"; + when '4' => ret := x"4"; + when '5' => ret := x"5"; + when '6' => ret := x"6"; + when '7' => ret := x"7"; + when '8' => ret := x"8"; + when '9' => ret := x"9"; + when 'a' | 'A' => ret := x"A"; + when 'b' | 'B' => ret := x"B"; + when 'c' | 'C' => ret := x"C"; + when 'd' | 'D' => ret := x"D"; + when 'e' | 'E' => ret := x"E"; + when 'f' | 'F' | '-' => ret := x"F"; + when others => ret := x"X"; + end case; + return ret; + end function to_hex; + +begin + + process (clk) is + begin + if rising_edge(clk) then + if (index < seq'high) then + index <= index + 1; + end if; + end if; + end process; + + data <= to_hex(seq(index)); + +end architecture rtl; + + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity issue is + port ( + clk : in std_logic + ); +end entity issue; + +architecture psl of issue is + + signal a, c : std_logic; + signal b : std_logic_vector(3 downto 0); + +begin + + -- 012345678901234567892345 + SEQ_A : entity work.sequencer generic map ("_-______________-_______") port map (clk, a); + SEQ_B : entity work.hex_sequencer generic map ("443334477444433355555555") port map (clk, b); + SEQ_C : entity work.sequencer generic map ("_____-___---______--_--_") port map (clk, c); + + + + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- Check for one possible value of b + -- Both assertions should hold + -- These are similar to waveform 2.6(a) on page 13 + -- in the book "A practical introduction to PSL" + + -- This assertion doesn't hold, assuming GHDL bug + -- Comparing to the next example, GHDL seems to have a problem with conditions + -- other than the given one (b = x"4"), even if the "enable" condition (b = "1") isn't true. + NEXT_EVENT_0_a : assert always ((a and b = x"4") -> next_event_a(c)[1 to 3](b = x"4")) + report "NEXT_EVENT_0_a failed"; + + -- Assertion holds. + NEXT_EVENT_1_a : assert always ((a and b = x"5") -> next_event_a(c)[1 to 4](b = x"5")) + report "NEXT_EVENT_1_a failed"; + + +end architecture psl; + +library ieee; + use ieee.std_logic_1164.all; + +use std.env.all; + + +entity test_issue is +end entity test_issue; + + +architecture sim of test_issue is + + signal clk : std_logic := '1'; + +begin + + + clk <= not clk after 500 ps; + + DUT : entity work.issue(psl) port map (clk); + + -- stop simulation after 30 cycles + process + variable index : natural := 30; + begin + loop + wait until rising_edge(clk); + index := index - 1; + exit when index = 0; + end loop; + stop(0); + end process; + + +end architecture sim; diff --git a/testsuite/gna/issue2157/repro.vhdl b/testsuite/gna/issue2157/repro.vhdl new file mode 100644 index 000000000..a3d67addd --- /dev/null +++ b/testsuite/gna/issue2157/repro.vhdl @@ -0,0 +1,20 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity repro is + port ( + a, c : std_logic; + b : std_logic_vector(3 downto 0); + clk : in std_logic + ); +end; + +architecture psl of repro is +begin + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + NEXT_EVENT_0_a : + assert always ((a and b = x"4") -> next_event_a(c)[1 to 2](b = x"4")) + report "NEXT_EVENT_0_a failed"; +end architecture psl; diff --git a/testsuite/gna/issue2157/repro2.vhdl b/testsuite/gna/issue2157/repro2.vhdl new file mode 100644 index 000000000..1b0fd5b0f --- /dev/null +++ b/testsuite/gna/issue2157/repro2.vhdl @@ -0,0 +1,34 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity repro is + port ( + a, c, d, e, f, x : std_logic; + b : std_logic_vector(3 downto 0); + clk : in std_logic + ); +end; + +architecture psl of repro is +begin + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + NEXT_EVENT_0_a : +-- assert always ((a and b = x"4") -> next_event_a(c)[1 to 2](b = x"4")) +-- assert always ((a and b = x"4") -> ({(not c)[*]; c; {[*0] | { (not c)[*]; c}}} |->(b = x"4"))) +-- assert always (a -> ({c; d; {[*0] | {(not e)[*];f}}} |->x)) +-- assert always (a -> ({c; {[*0] | {d[*]; e}}} |->x)) +-- assert always ({c; {[*0] | {d[*]; e}}} |->x) +-- assert never {c; {[*0] | {d[*]; e}}} +-- assert always ({c | {c; d[*]; e}} |->x) +-- assert always ({c; {d[*]; e}} |->x) + report "NEXT_EVENT_0_a failed"; +end architecture psl; + +-- next_event_a(b)[k:l](p) = {b[->k:l]} |-> p +-- b[->k:l] = b[->k] | ... | b[->l] +-- = {!b[*];b}[*k:l] +-- s[*i:j] = s[*i] | ... | s[*j] + +-- next_event_a(b)[k:l](p) = {{!b[*];b}[*k] | .. | {!b[*];b}[*l] } |-> p diff --git a/testsuite/gna/issue2157/testsuite.sh b/testsuite/gna/issue2157/testsuite.sh new file mode 100755 index 000000000..197a21ff9 --- /dev/null +++ b/testsuite/gna/issue2157/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze issue.vhdl +elab_simulate issue + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2157/trepro.vhdl b/testsuite/gna/issue2157/trepro.vhdl new file mode 100644 index 000000000..9c0ddf2e1 --- /dev/null +++ b/testsuite/gna/issue2157/trepro.vhdl @@ -0,0 +1,140 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity sequencer is + generic ( + seq : string + ); + port ( + clk : in std_logic; + data : out std_logic + ); +end entity sequencer; + +architecture rtl of sequencer is + + signal index : natural := seq'low; + + function to_bit (a : in character) return std_logic is + variable ret : std_logic; + begin + case a is + when '0' | '_' => ret := '0'; + when '1' | '-' => ret := '1'; + when others => ret := 'X'; + end case; + return ret; + end function to_bit; + +begin + + process (clk) is + begin + if rising_edge(clk) then + if (index < seq'high) then + index <= index + 1; + end if; + end if; + end process; + + data <= to_bit(seq(index)); + +end architecture rtl; + +library ieee; + use ieee.std_logic_1164.all; + +entity hex_sequencer is + generic ( + seq : string + ); + port ( + clk : in std_logic; + data : out std_logic_vector(3 downto 0) + ); +end entity hex_sequencer; + +architecture rtl of hex_sequencer is + + signal index : natural := seq'low; + + function to_hex (a : in character) return std_logic_vector is + variable ret : std_logic_vector(3 downto 0); + begin + case a is + when '0' | '_' => ret := x"0"; + when '1' => ret := x"1"; + when '2' => ret := x"2"; + when '3' => ret := x"3"; + when '4' => ret := x"4"; + when '5' => ret := x"5"; + when '6' => ret := x"6"; + when '7' => ret := x"7"; + when '8' => ret := x"8"; + when '9' => ret := x"9"; + when 'a' | 'A' => ret := x"A"; + when 'b' | 'B' => ret := x"B"; + when 'c' | 'C' => ret := x"C"; + when 'd' | 'D' => ret := x"D"; + when 'e' | 'E' => ret := x"E"; + when 'f' | 'F' | '-' => ret := x"F"; + when others => ret := x"X"; + end case; + return ret; + end function to_hex; + +begin + + process (clk) is + begin + if rising_edge(clk) then + if (index < seq'high) then + index <= index + 1; + end if; + end if; + end process; + + data <= to_hex(seq(index)); + +end architecture rtl; + + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity issue is +end entity issue; + +architecture psl of issue is + + signal a, c : std_logic; + signal b : std_logic_vector(3 downto 0); + + signal clk : std_logic := '1'; + +begin + + -- 012345678901234567892345 + SEQ_A : entity work.sequencer generic map ("_-______________-_______") port map (clk, a); + SEQ_B : entity work.hex_sequencer generic map ("443334477444433355555555") port map (clk, b); + SEQ_C : entity work.sequencer generic map ("_____-___---______--_--_") port map (clk, c); + + + inst : entity work.repro + port map (a => a, b => b, c => c, clk => clk); + + clk <= not clk after 500 ps; + + -- stop simulation after 30 cycles + process + variable index : natural := 30; + begin + loop + wait until rising_edge(clk); + index := index - 1; + exit when index = 0; + end loop; + std.env.stop(0); + end process; +end architecture psl; -- cgit v1.2.3