From 920e4c91bf32a292809f1afa4f96f7ec1312a9c7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 13 Dec 2020 18:35:52 +0100
Subject: testsuite/synth: more tests for #1534

---
 testsuite/synth/issue1534/ent2.vhdl  | 13 +++++++++++++
 testsuite/synth/issue1534/xor01.vhdl | 13 +++++++++++++
 testsuite/synth/issue1534/xor02.vhdl | 15 +++++++++++++++
 3 files changed, 41 insertions(+)
 create mode 100644 testsuite/synth/issue1534/ent2.vhdl
 create mode 100644 testsuite/synth/issue1534/xor01.vhdl
 create mode 100644 testsuite/synth/issue1534/xor02.vhdl

(limited to 'testsuite')

diff --git a/testsuite/synth/issue1534/ent2.vhdl b/testsuite/synth/issue1534/ent2.vhdl
new file mode 100644
index 000000000..cf20daf85
--- /dev/null
+++ b/testsuite/synth/issue1534/ent2.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent2 is
+    port (
+        o: out std_ulogic_vector(3 downto 0)
+    );
+end entity;
+
+architecture arch of ent2 is
+begin
+    o <= to_stdulogicvector(bit_vector'("0101"));
+end architecture;
diff --git a/testsuite/synth/issue1534/xor01.vhdl b/testsuite/synth/issue1534/xor01.vhdl
new file mode 100644
index 000000000..41a8e252d
--- /dev/null
+++ b/testsuite/synth/issue1534/xor01.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xor01 is
+    port (
+        o: out bit_vector(3 downto 0)
+    );
+end entity;
+
+architecture arch of xor01 is
+begin
+    o <= bit_vector'("1100") xor bit_vector'("1010");
+end architecture;
diff --git a/testsuite/synth/issue1534/xor02.vhdl b/testsuite/synth/issue1534/xor02.vhdl
new file mode 100644
index 000000000..9d1c63319
--- /dev/null
+++ b/testsuite/synth/issue1534/xor02.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xor02 is
+    port (
+        o: out bit
+    );
+end entity;
+
+architecture arch of xor02 is
+    constant x: bit_vector(0 to 0) := "1";
+    constant y: bit_vector(0 to 0) := "0";
+begin
+    o <= x(0) xor y(0);
+end architecture;
-- 
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