From 8e8bcd08a82757efa50e1ab9f58ab8186faccccb Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 30 Apr 2021 21:16:12 +0200 Subject: testsuite/synth: add tests for concurrent dff --- testsuite/synth/dff05/dff01.vhdl | 13 +++++++++ testsuite/synth/dff05/dff02.vhdl | 14 ++++++++++ testsuite/synth/dff05/tb_dff01.vhdl | 40 +++++++++++++++++++++++++++ testsuite/synth/dff05/tb_dff02.vhdl | 55 +++++++++++++++++++++++++++++++++++++ testsuite/synth/dff05/testsuite.sh | 9 ++++++ 5 files changed, 131 insertions(+) create mode 100644 testsuite/synth/dff05/dff01.vhdl create mode 100644 testsuite/synth/dff05/dff02.vhdl create mode 100644 testsuite/synth/dff05/tb_dff01.vhdl create mode 100644 testsuite/synth/dff05/tb_dff02.vhdl create mode 100755 testsuite/synth/dff05/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/synth/dff05/dff01.vhdl b/testsuite/synth/dff05/dff01.vhdl new file mode 100644 index 000000000..f16e614dc --- /dev/null +++ b/testsuite/synth/dff05/dff01.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff01 is + port (q : out std_logic; + d : std_logic; + clk : std_logic); +end dff01; + +architecture behav of dff01 is +begin + q <= d when rising_edge (clk); +end behav; diff --git a/testsuite/synth/dff05/dff02.vhdl b/testsuite/synth/dff05/dff02.vhdl new file mode 100644 index 000000000..09d10e29c --- /dev/null +++ b/testsuite/synth/dff05/dff02.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff02 is + port (q : out std_logic; + d : std_logic; + clk : std_logic; + rst : std_logic); +end dff02; + +architecture behav of dff02 is +begin + q <= '0' when rst = '1' else d when rising_edge (clk); +end behav; diff --git a/testsuite/synth/dff05/tb_dff01.vhdl b/testsuite/synth/dff05/tb_dff01.vhdl new file mode 100644 index 000000000..7008a8b95 --- /dev/null +++ b/testsuite/synth/dff05/tb_dff01.vhdl @@ -0,0 +1,40 @@ +entity tb_dff01 is +end tb_dff01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_dff01 is + signal clk : std_logic; + signal din : std_logic; + signal dout : std_logic; +begin + dut: entity work.dff01 + port map ( + q => dout, + d => din, + clk => clk); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + din <= '0'; + pulse; + assert dout = '0' severity failure; + din <= '1'; + pulse; + assert dout = '1' severity failure; + pulse; + assert dout = '1' severity failure; + din <= '0'; + pulse; + assert dout = '0' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/dff05/tb_dff02.vhdl b/testsuite/synth/dff05/tb_dff02.vhdl new file mode 100644 index 000000000..d22a3bd9c --- /dev/null +++ b/testsuite/synth/dff05/tb_dff02.vhdl @@ -0,0 +1,55 @@ +entity tb_dff02 is +end tb_dff02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_dff02 is + signal clk : std_logic; + signal din : std_logic; + signal dout : std_logic; + signal rst : std_logic; +begin + dut: entity work.dff02 + port map ( + q => dout, + d => din, + clk => clk, + rst => rst); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + rst <= '1'; + wait for 1 ns; + assert dout = '0' severity failure; + + rst <= '0'; + din <= '1'; + pulse; + assert dout = '1' severity failure; + + din <= '0'; + pulse; + assert dout = '0' severity failure; + + pulse; + assert dout = '0' severity failure; + + din <= '1'; + pulse; + assert dout = '1' severity failure; + + rst <= '1'; + wait for 1 ns; + assert dout = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/dff05/testsuite.sh b/testsuite/synth/dff05/testsuite.sh new file mode 100755 index 000000000..a86174437 --- /dev/null +++ b/testsuite/synth/dff05/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in dff01 dff02; do + synth_tb $t +done + +echo "Test successful" -- cgit v1.2.3