From 83a5f96469efc690da3e86e9983b3dfc84f4fa3c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 18 Feb 2022 06:39:49 +0100 Subject: testsuite/synth: add a test for #1968 --- testsuite/synth/issue1968/dummy.vhdl | 23 +++++++ testsuite/synth/issue1968/dummy_pkg.vhdl | 110 +++++++++++++++++++++++++++++++ testsuite/synth/issue1968/testsuite.sh | 8 +++ 3 files changed, 141 insertions(+) create mode 100644 testsuite/synth/issue1968/dummy.vhdl create mode 100644 testsuite/synth/issue1968/dummy_pkg.vhdl create mode 100755 testsuite/synth/issue1968/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/synth/issue1968/dummy.vhdl b/testsuite/synth/issue1968/dummy.vhdl new file mode 100644 index 000000000..2aa42e172 --- /dev/null +++ b/testsuite/synth/issue1968/dummy.vhdl @@ -0,0 +1,23 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.NUMERIC_STD.all; +use work.dummy_pkg.all; + +entity dummy is + port ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ); +end dummy; + +architecture rtl of dummy is +begin + +-- this_works(A_i, B_i, C_i, o); + + this_doesnt_work(A_i, B_i, C_i, o); + +end rtl; diff --git a/testsuite/synth/issue1968/dummy_pkg.vhdl b/testsuite/synth/issue1968/dummy_pkg.vhdl new file mode 100644 index 000000000..bc9c3244f --- /dev/null +++ b/testsuite/synth/issue1968/dummy_pkg.vhdl @@ -0,0 +1,110 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.NUMERIC_STD.all; + +package dummy_pkg is + type wordarray is array (natural range<>) of std_logic_vector(31 downto 0); + + procedure p_csa ( + variable A: in std_logic_vector(31 downto 0); + variable B: in std_logic_vector(31 downto 0); + variable Ci: in std_logic_vector(31 downto 0); + variable S: out std_logic_vector(31 downto 0); + variable Co: out std_logic_vector(31 downto 0) + ); + + function f_csa ( + A : std_logic_vector(31 downto 0); + B: std_logic_vector(31 downto 0); + Ci: std_logic_vector(31 downto 0) + ) return wordarray; + + procedure this_works ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ); + + procedure this_doesnt_work ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ); + +end dummy_pkg; + +package body dummy_pkg is + + procedure p_csa ( + variable A: in std_logic_vector(31 downto 0); + variable B: in std_logic_vector(31 downto 0); + variable Ci: in std_logic_vector(31 downto 0); + variable S: out std_logic_vector(31 downto 0); + variable Co: out std_logic_vector(31 downto 0) + ) is + variable Co_tmp : std_logic_vector(32 downto 0); + begin + S := A xor B xor Ci; + Co_tmp := ((A and B) or (B and Ci) or (A and Ci)) & '0'; + Co := Co_tmp(31 downto 0); + end procedure p_csa; + + function f_csa ( + A : std_logic_vector(31 downto 0); + B: std_logic_vector(31 downto 0); + Ci: std_logic_vector(31 downto 0) + ) return wordarray is + variable r : wordarray(1 downto 0); + variable Co_tmp : std_logic_vector(32 downto 0); + begin + r(0) := A xor B xor Ci; + Co_tmp := ((A and B) or (B and Ci) or (A and Ci)) & '0'; + r(1) := Co_tmp(31 downto 0); + return r; + end function; + + procedure this_works ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ) is + variable a : std_logic_vector(31 downto 0); + variable b : std_logic_vector(31 downto 0); + variable c : std_logic_vector(31 downto 0); + variable r0 : wordarray(1 downto 0); + variable s0 : std_logic_vector(31 downto 0); + variable c0 : std_logic_vector(31 downto 0); + begin + a := A_i; + b := B_i; + c := C_i; + r0 := f_csa(a, b, c); + s0 := r0(0); + c0 := r0(1); + o <= s0 + c0; + end procedure this_works; + + procedure this_doesnt_work ( + signal A_i : in std_logic_vector(31 downto 0); + signal B_i : in std_logic_vector(31 downto 0); + signal C_i : in std_logic_vector(31 downto 0); + signal o : out std_logic_vector(31 downto 0) + ) is + variable a : std_logic_vector(31 downto 0); + variable b : std_logic_vector(31 downto 0); + variable c : std_logic_vector(31 downto 0); + variable s0 : std_logic_vector(31 downto 0); + variable c0 : std_logic_vector(31 downto 0); + begin + a := A_i; + b := B_i; + c := C_i; + p_csa(a, b, c, s0, c0); + o <= s0 + c0; + end procedure this_doesnt_work; + +end dummy_pkg; diff --git a/testsuite/synth/issue1968/testsuite.sh b/testsuite/synth/issue1968/testsuite.sh new file mode 100755 index 000000000..9b5b1ea72 --- /dev/null +++ b/testsuite/synth/issue1968/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth -fsynopsys dummy_pkg.vhdl dummy.vhdl -e > syn_dummy.vhdl + +echo "Test successful" -- cgit v1.2.3