From 809c2a886a3adaa565c6b3877df04c09204463ab Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 13 May 2021 09:53:20 +0200
Subject: testsuite/gna: add a test for #641

From SynthWorks.
---
 .../test_2b_record_subtype_alias/TbTest.vhd        | 35 ++++++++++++++++++++++
 .../issue641/test_2b_record_subtype_alias/Test.vhd | 33 ++++++++++++++++++++
 .../test_2b_record_subtype_alias/TestPkg.vhd       | 10 +++++++
 testsuite/gna/issue641/testsuite.sh                |  9 ++++++
 4 files changed, 87 insertions(+)
 create mode 100644 testsuite/gna/issue641/test_2b_record_subtype_alias/TbTest.vhd
 create mode 100644 testsuite/gna/issue641/test_2b_record_subtype_alias/Test.vhd
 create mode 100644 testsuite/gna/issue641/test_2b_record_subtype_alias/TestPkg.vhd

(limited to 'testsuite')

diff --git a/testsuite/gna/issue641/test_2b_record_subtype_alias/TbTest.vhd b/testsuite/gna/issue641/test_2b_record_subtype_alias/TbTest.vhd
new file mode 100644
index 000000000..700e9a82a
--- /dev/null
+++ b/testsuite/gna/issue641/test_2b_record_subtype_alias/TbTest.vhd
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.TestPkg.all ;
+
+entity TbTest is
+end entity TbTest;
+
+architecture rtl of TbTest is
+
+  component test is
+    port(
+      input : in ARecType
+    );
+  end component test;
+
+  signal Fred : ARecType( A(7 downto 0)) ;
+begin
+  test_1 : test
+    port map (
+      input => Fred
+    );
+
+  process
+  begin
+    Fred.A <= X"00" ;
+    wait for 1 ns ;
+    for i in 1 to 10 loop
+      Fred.A <= X"00" + i ;
+      wait for 1 ns ;
+    end loop ;
+    std.env.stop ;
+  end process ;
+end architecture;
diff --git a/testsuite/gna/issue641/test_2b_record_subtype_alias/Test.vhd b/testsuite/gna/issue641/test_2b_record_subtype_alias/Test.vhd
new file mode 100644
index 000000000..7e22615d2
--- /dev/null
+++ b/testsuite/gna/issue641/test_2b_record_subtype_alias/Test.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.TestPkg.all ;
+
+entity test is
+  port(
+    input : in ARecType
+  );
+end entity;
+
+architecture rtl of test is
+  signal copy : input'subtype;   -- fails
+--  signal copy : ARecType(A(input.A'range)) ; -- Works
+
+  alias B is copy ;
+
+--  Inconjunction with input'subtype the following all fail.
+--  alias B : ARecType(A(input.A'range)) is copy ;  -- with failing case, causes runtime bounds check failure
+--  alias B : ARecType(A(7 downto 0)) is copy ;
+--  subtype BType is AReCType(A(7 downto 0)) ;
+--    alias B : BType is copy ;
+begin
+  copy <= input ;
+
+  process
+  begin
+    wait on copy ;  -- Suppress first run
+    report "Copy.A, B.A = " & to_hstring(Copy.A) & ", " & to_hstring(B.A) ;
+  end process ;
+
+end architecture;
diff --git a/testsuite/gna/issue641/test_2b_record_subtype_alias/TestPkg.vhd b/testsuite/gna/issue641/test_2b_record_subtype_alias/TestPkg.vhd
new file mode 100644
index 000000000..24eeaabf4
--- /dev/null
+++ b/testsuite/gna/issue641/test_2b_record_subtype_alias/TestPkg.vhd
@@ -0,0 +1,10 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package TestPkg is
+  type ARecType is record
+    A : unsigned ;
+  end record ARecType ; 
+
+end package TestPkg ; 
diff --git a/testsuite/gna/issue641/testsuite.sh b/testsuite/gna/issue641/testsuite.sh
index 88c716c6b..88a030c79 100755
--- a/testsuite/gna/issue641/testsuite.sh
+++ b/testsuite/gna/issue641/testsuite.sh
@@ -13,4 +13,13 @@ done
 
 clean
 
+# From synthworks
+
+analyze test_2b_record_subtype_alias/TestPkg.vhd
+analyze test_2b_record_subtype_alias/Test.vhd
+analyze test_2b_record_subtype_alias/TbTest.vhd
+simulate TbTest
+
+clean
+
 echo "Test successful"
-- 
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