From 7c6d865f8c663917e943708a9032af297e17e0c7 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 30 Apr 2020 07:36:58 +0200 Subject: testsuite/synth: add tests for #1271 --- testsuite/synth/issue1271/issue.vhdl | 14 ++++++++++++++ testsuite/synth/issue1271/issue2.vhdl | 22 ++++++++++++++++++++++ testsuite/synth/issue1271/testsuite.sh | 8 ++++++++ 3 files changed, 44 insertions(+) create mode 100644 testsuite/synth/issue1271/issue.vhdl create mode 100644 testsuite/synth/issue1271/issue2.vhdl create mode 100755 testsuite/synth/issue1271/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/synth/issue1271/issue.vhdl b/testsuite/synth/issue1271/issue.vhdl new file mode 100644 index 000000000..ee222b0b5 --- /dev/null +++ b/testsuite/synth/issue1271/issue.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity issue is + port + (i_foo : in std_logic; + o_foo : out std_logic); +end entity issue; + +architecture beh of issue is + constant k_foo : std_logic := i_foo; +begin + o_foo <= k_foo xor '0'; +end architecture; diff --git a/testsuite/synth/issue1271/issue2.vhdl b/testsuite/synth/issue1271/issue2.vhdl new file mode 100644 index 000000000..1dd359c6c --- /dev/null +++ b/testsuite/synth/issue1271/issue2.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity issue is + port + (i_foo : in std_logic; + o_foo : out std_logic; + clock : in std_logic); +end entity issue; + +architecture beh of issue is +begin + process (clock) + variable v_foo : std_logic := i_foo; + begin + -- works without the if + if rising_edge (clock) then + v_foo := v_foo xor v_foo; + o_foo <= v_foo; + end if; + end process; +end architecture; diff --git a/testsuite/synth/issue1271/testsuite.sh b/testsuite/synth/issue1271/testsuite.sh new file mode 100755 index 000000000..b352bb675 --- /dev/null +++ b/testsuite/synth/issue1271/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_failure issue.vhdl -e +synth_failure issue2.vhdl -e + +echo "Test successful" -- cgit v1.2.3