From 76404f71df0f7c1037b190a3cf23bad84bc4c84b Mon Sep 17 00:00:00 2001
From: umarcor <unai.martinezcorral@ehu.eus>
Date: Fri, 23 Apr 2021 02:37:19 +0200
Subject: testsuite/gna/issue668: use ghw_diff (#1740)

---
 testsuite/gna/issue668/golden_wb_demux_tb.txt |  0
 testsuite/gna/issue668/tb.vhdl                | 54 ---------------------------
 testsuite/gna/issue668/testsuite.sh           | 25 +++++--------
 testsuite/gna/issue668/wb_demux_tb.vhdl       | 54 +++++++++++++++++++++++++++
 4 files changed, 64 insertions(+), 69 deletions(-)
 create mode 100644 testsuite/gna/issue668/golden_wb_demux_tb.txt
 delete mode 100644 testsuite/gna/issue668/tb.vhdl
 create mode 100644 testsuite/gna/issue668/wb_demux_tb.vhdl

(limited to 'testsuite')

diff --git a/testsuite/gna/issue668/golden_wb_demux_tb.txt b/testsuite/gna/issue668/golden_wb_demux_tb.txt
new file mode 100644
index 000000000..e69de29bb
diff --git a/testsuite/gna/issue668/tb.vhdl b/testsuite/gna/issue668/tb.vhdl
deleted file mode 100644
index 768038201..000000000
--- a/testsuite/gna/issue668/tb.vhdl
+++ /dev/null
@@ -1,54 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package wishbone_pkg is
---./wb_demux_tb:internal error: wave.create_type
-	type t_wishbone_master_out is record
-		dat : std_logic_vector;
-	end record;
-	subtype t_wishbone_slave_in is t_wishbone_master_out;
-end wishbone_pkg;
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-library work;
-use work.wishbone_pkg.all;
-
-entity wb_demux is
-    Port (
-    	wbs_i	: in t_wishbone_slave_in
-    );
-end wb_demux;
-architecture full_regs of wb_demux is
-begin
-end full_regs;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.wishbone_pkg.all;
-
-entity wb_demux_tb is
-end entity;
-architecture bench of wb_demux_tb is
-	signal wbs_i : t_wishbone_slave_in(
-		dat(32-1 downto 0)
-	);
-begin
-	stimulus : process
-	begin
-		wbs_i.dat <= x"deadbeef";
-		wait for 100 ns;
-		report "pass" severity note;
-		wait;
-	end process;
-
-	dut : entity work.wb_demux
-	port map (
-		wbs_i => wbs_i
-	);
-end architecture;
-
diff --git a/testsuite/gna/issue668/testsuite.sh b/testsuite/gna/issue668/testsuite.sh
index 19b6004b5..62af85327 100755
--- a/testsuite/gna/issue668/testsuite.sh
+++ b/testsuite/gna/issue668/testsuite.sh
@@ -3,23 +3,18 @@
 . ../../testenv.sh
 
 export GHDL_STD_FLAGS=--std=08
-analyze tb.vhdl
-elab wb_demux_tb
+for item in wb_demux_tb repro2; do
+  analyze "$item".vhdl
+  elab "$item"
 
-if ghdl_has_feature wb_demux_tb ghw; then
-  simulate wb_demux_tb --dump-rti
-  simulate wb_demux_tb --wave=w.ghw
-fi
-
-analyze repro2.vhdl
-elab repro2
-if ghdl_has_feature repro2 ghw; then
-  simulate repro2 --dump-rti
-  simulate repro2 --wave=w.ghw
-fi
+  if ghdl_has_feature "$item" ghw; then
+    elab_simulate "$item" --dump-rti
+    elab_simulate "$item" --wave="$item".ghw
+    ghw_diff "$item"
+    rm -f "$item".txt "$item".ghw
+  fi
+done
 
 clean
 
-rm -f w.ghw
-
 echo "Test successful"
diff --git a/testsuite/gna/issue668/wb_demux_tb.vhdl b/testsuite/gna/issue668/wb_demux_tb.vhdl
new file mode 100644
index 000000000..768038201
--- /dev/null
+++ b/testsuite/gna/issue668/wb_demux_tb.vhdl
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package wishbone_pkg is
+--./wb_demux_tb:internal error: wave.create_type
+	type t_wishbone_master_out is record
+		dat : std_logic_vector;
+	end record;
+	subtype t_wishbone_slave_in is t_wishbone_master_out;
+end wishbone_pkg;
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library work;
+use work.wishbone_pkg.all;
+
+entity wb_demux is
+    Port (
+    	wbs_i	: in t_wishbone_slave_in
+    );
+end wb_demux;
+architecture full_regs of wb_demux is
+begin
+end full_regs;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.wishbone_pkg.all;
+
+entity wb_demux_tb is
+end entity;
+architecture bench of wb_demux_tb is
+	signal wbs_i : t_wishbone_slave_in(
+		dat(32-1 downto 0)
+	);
+begin
+	stimulus : process
+	begin
+		wbs_i.dat <= x"deadbeef";
+		wait for 100 ns;
+		report "pass" severity note;
+		wait;
+	end process;
+
+	dut : entity work.wb_demux
+	port map (
+		wbs_i => wbs_i
+	);
+end architecture;
+
-- 
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