From 72b5a66438052bf7e089b7f5ab1fee3462aa2a81 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 22 Apr 2020 19:24:11 +0200
Subject: testsuite/synth: add a test for previous commit

---
 testsuite/synth/mem01/sram05.vhdl    | 34 ++++++++++++++
 testsuite/synth/mem01/tb_sram05.vhdl | 87 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/mem01/testsuite.sh   |  2 +-
 3 files changed, 122 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/mem01/sram05.vhdl
 create mode 100644 testsuite/synth/mem01/tb_sram05.vhdl

(limited to 'testsuite')

diff --git a/testsuite/synth/mem01/sram05.vhdl b/testsuite/synth/mem01/sram05.vhdl
new file mode 100644
index 000000000..a634e0b19
--- /dev/null
+++ b/testsuite/synth/mem01/sram05.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sram05 is
+  port (
+    rst : std_logic;
+    clk_i  : std_logic;
+    addr_i : std_logic_vector(3 downto 0);
+    data_i : std_logic_vector(7 downto 0);
+    data_o : out std_logic_vector(7 downto 0);
+    wen_i   : std_logic);
+end sram05;
+
+architecture behav of sram05 is
+begin
+  process (clk_i, addr_i)
+    type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
+    variable mem : mem_type;
+    variable addr : natural range mem_type'range;
+  begin
+    if rising_edge(clk_i) then
+      if rst = '1' then
+        null;
+      else
+        addr := to_integer (unsigned (addr_i));
+        if wen_i = '1' then
+          mem (addr) := data_i;
+        end if;
+        data_o <= mem (addr);
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/tb_sram05.vhdl b/testsuite/synth/mem01/tb_sram05.vhdl
new file mode 100644
index 000000000..25b96edb3
--- /dev/null
+++ b/testsuite/synth/mem01/tb_sram05.vhdl
@@ -0,0 +1,87 @@
+entity tb_sram05 is
+end tb_sram05;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sram05 is
+  signal rst : std_logic;
+  signal addr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal wen : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.sram05
+    port map (rst => rst, clk_i => clk,
+              addr_i => addr, data_i => wdat, data_o => rdat,
+              wen_i => wen);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '0';
+
+    --  [0] := x03
+    addr <= "0000";
+    wdat <= x"03";
+    wen <= '1';
+    pulse;
+    assert rdat = x"03" severity failure;
+
+    --  [0] := x41
+    wdat <= x"41";
+    pulse;
+    assert rdat = x"41" severity failure;
+
+    --  [4] := x07
+    addr <= "0100";
+    wdat <= x"07";
+    wait for 1 ns;
+    pulse;
+    assert rdat = x"07" severity failure;
+
+    --  Not en.
+    addr <= "0000";
+    wen <= '0';
+    pulse;
+    assert rdat = x"41" severity failure;
+
+    --  [4] := x23
+    wen <= '1';
+    addr <= "0100";
+    wdat <= x"23";
+    wait for 1 ns;
+    pulse;
+    assert rdat = x"23" severity failure;
+
+    --  Reset
+    rst <= '1';
+    addr <= "0100";
+    wdat <= x"ff";
+    wait for 1 ns;
+    pulse;
+    assert rdat = x"23" severity failure;
+
+    --  None
+    rst <= '0';
+    wen <= '0';
+    addr <= "0000";
+    wdat <= x"c5";
+    pulse;
+    assert rdat = x"41" severity failure;
+
+    --  None
+    addr <= "0100";
+    pulse;
+    assert rdat = x"23" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem01/testsuite.sh b/testsuite/synth/mem01/testsuite.sh
index 315ff4f4e..186456831 100755
--- a/testsuite/synth/mem01/testsuite.sh
+++ b/testsuite/synth/mem01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in rom1 srom01 sram01 sram02 sram03 dpram1 dpram2 dpram3; do
+for t in rom1 srom01 sram01 sram02 sram03 sram05 dpram1 dpram2 dpram3; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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