From 59c6890377b635797dff61346a780b4d23436736 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 28 Sep 2019 23:21:05 +0200
Subject: testsuite/synth: add testcase for #945

---
 testsuite/synth/issue945/ent.vhdl     |  9 +++++++++
 testsuite/synth/issue945/syn_ent.vhdl | 13 +++++++++++++
 testsuite/synth/issue945/testsuite.sh |  8 ++++++++
 3 files changed, 30 insertions(+)
 create mode 100644 testsuite/synth/issue945/ent.vhdl
 create mode 100644 testsuite/synth/issue945/syn_ent.vhdl
 create mode 100755 testsuite/synth/issue945/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue945/ent.vhdl b/testsuite/synth/issue945/ent.vhdl
new file mode 100644
index 000000000..ff2ce407f
--- /dev/null
+++ b/testsuite/synth/issue945/ent.vhdl
@@ -0,0 +1,9 @@
+entity ent is
+end ent;
+
+architecture a of ent is
+    signal test : bit;
+    alias a1 : bit is test;
+    alias a2 : bit is a1;
+begin
+end a;
diff --git a/testsuite/synth/issue945/syn_ent.vhdl b/testsuite/synth/issue945/syn_ent.vhdl
new file mode 100644
index 000000000..3477d2338
--- /dev/null
+++ b/testsuite/synth/issue945/syn_ent.vhdl
@@ -0,0 +1,13 @@
+entity ent is
+end ent;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture rtl of ent is
+  signal test : std_logic;
+begin
+  -- ent.vhdl:5:12
+  test <= <unassigned>; -- (signal)
+end rtl;
diff --git a/testsuite/synth/issue945/testsuite.sh b/testsuite/synth/issue945/testsuite.sh
new file mode 100755
index 000000000..6c14ee73a
--- /dev/null
+++ b/testsuite/synth/issue945/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth ent.vhdl -e ent > syn_ent.vhdl
+clean
+
+echo "Test successful"
-- 
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