From 4974ee462a6674d4c85d4178c57e22a9ae7e1cba Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 19 Feb 2021 08:59:35 +0100
Subject: testsuite/synth: add a test for #1650

---
 testsuite/synth/issue1650/debounce.vhdl | 43 +++++++++++++++++++++++++++++++++
 testsuite/synth/issue1650/testsuite.sh  |  9 +++++++
 2 files changed, 52 insertions(+)
 create mode 100644 testsuite/synth/issue1650/debounce.vhdl
 create mode 100755 testsuite/synth/issue1650/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue1650/debounce.vhdl b/testsuite/synth/issue1650/debounce.vhdl
new file mode 100644
index 000000000..0ea40d1a5
--- /dev/null
+++ b/testsuite/synth/issue1650/debounce.vhdl
@@ -0,0 +1,43 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity debounce is
+	generic (
+		N_CYCLES: integer := 255
+	);
+	port
+	(
+		clk: in std_ulogic;
+		reset_n: in std_ulogic;
+		debounce_in: in std_ulogic;
+		debounced_out: buffer std_ulogic
+	);
+end debounce;
+
+architecture rtl of debounce is
+    signal counter: integer range 0 to N_CYCLES;
+    signal previous_debounce_in: std_ulogic := '0';
+begin
+	process(clk, reset_n)
+	begin
+        if (reset_n = '0') then
+            previous_debounce_in <= '0';
+			debounced_out <= '0';
+			counter <= 0;
+        elsif rising_edge(clk) then
+
+			if debounce_in = previous_debounce_in then
+				if counter = N_CYCLES then
+					debounced_out <= debounce_in;
+				else
+					counter <= counter + 1;
+				end if;
+			else
+				counter <= 0;
+            end if;
+
+            previous_debounce_in <= debounce_in;
+		end if;
+	end process;
+end rtl;
diff --git a/testsuite/synth/issue1650/testsuite.sh b/testsuite/synth/issue1650/testsuite.sh
new file mode 100755
index 000000000..190a675ec
--- /dev/null
+++ b/testsuite/synth/issue1650/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_failure --vendor-library=missing_lib debounce.vhdl -e
+
+synth_only debounce
+
+echo "Test successful"
-- 
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