From 4670aa3c0f4f9be576abba68daa17f2667599524 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 28 Sep 2019 07:23:19 +0200 Subject: testsuite/synth: add if01 --- testsuite/synth/if01/if01.vhdl | 21 +++++++++++++++++++++ testsuite/synth/if01/tb_if01.vhdl | 38 ++++++++++++++++++++++++++++++++++++++ testsuite/synth/if01/testsuite.sh | 16 ++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 testsuite/synth/if01/if01.vhdl create mode 100644 testsuite/synth/if01/tb_if01.vhdl create mode 100755 testsuite/synth/if01/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/synth/if01/if01.vhdl b/testsuite/synth/if01/if01.vhdl new file mode 100644 index 000000000..0e1084a12 --- /dev/null +++ b/testsuite/synth/if01/if01.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity if01 is + port (c0, c1 : std_logic; + r : out std_logic); +end if01; + +architecture behav of if01 is +begin + process (c0, c1) + begin + r <= '0'; + if c0 = '1' then + if c1 = '1' then + r <= '1'; + end if; + end if; + end process; +end behav; diff --git a/testsuite/synth/if01/tb_if01.vhdl b/testsuite/synth/if01/tb_if01.vhdl new file mode 100644 index 000000000..2c608137d --- /dev/null +++ b/testsuite/synth/if01/tb_if01.vhdl @@ -0,0 +1,38 @@ +entity tb_if01 is +end tb_if01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_if01 is + signal c0, c1 : std_logic; + signal r : std_logic; +begin + dut: entity work.if01 + port map (c0, c1, r); + + process + begin + c0 <= '1'; + c1 <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + c0 <= '0'; + c1 <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + c0 <= '1'; + c1 <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + c0 <= '0'; + c1 <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/if01/testsuite.sh b/testsuite/synth/if01/testsuite.sh new file mode 100755 index 000000000..061e1924a --- /dev/null +++ b/testsuite/synth/if01/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in if01; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" -- cgit v1.2.3