From 3fca9501e16d90cc268b641ae165a22afdacf5e8 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 25 Sep 2019 07:37:33 +0200
Subject: testsuite/synth: add testcase for #937

---
 testsuite/synth/issue937/bnot.vhdl    | 12 ++++++++++++
 testsuite/synth/issue937/enot.vhdl    | 20 ++++++++++++++++++++
 testsuite/synth/issue937/ent.vhdl     | 19 +++++++++++++++++++
 testsuite/synth/issue937/tb_bnot.vhdl | 23 +++++++++++++++++++++++
 testsuite/synth/issue937/tb_enot.vhdl | 31 +++++++++++++++++++++++++++++++
 testsuite/synth/issue937/testsuite.sh | 16 ++++++++++++++++
 6 files changed, 121 insertions(+)
 create mode 100644 testsuite/synth/issue937/bnot.vhdl
 create mode 100644 testsuite/synth/issue937/enot.vhdl
 create mode 100644 testsuite/synth/issue937/ent.vhdl
 create mode 100644 testsuite/synth/issue937/tb_bnot.vhdl
 create mode 100644 testsuite/synth/issue937/tb_enot.vhdl
 create mode 100755 testsuite/synth/issue937/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue937/bnot.vhdl b/testsuite/synth/issue937/bnot.vhdl
new file mode 100644
index 000000000..6c21b2c2f
--- /dev/null
+++ b/testsuite/synth/issue937/bnot.vhdl
@@ -0,0 +1,12 @@
+entity bnot is
+    port (
+        i : in bit;
+        o : out bit
+    );
+end entity;
+
+architecture a of bnot is
+begin
+  o <= not i;
+end;
+
diff --git a/testsuite/synth/issue937/enot.vhdl b/testsuite/synth/issue937/enot.vhdl
new file mode 100644
index 000000000..ea583d4ed
--- /dev/null
+++ b/testsuite/synth/issue937/enot.vhdl
@@ -0,0 +1,20 @@
+entity enot is
+    port (
+        i : in bit;
+        x : in boolean;
+        o : out bit
+    );
+end entity;
+
+architecture a of enot is
+begin
+    process(i, x)
+    begin
+        if not x then
+            o <= i;
+        else
+            o <= '0';
+        end if;
+    end process;
+end;
+
diff --git a/testsuite/synth/issue937/ent.vhdl b/testsuite/synth/issue937/ent.vhdl
new file mode 100644
index 000000000..e96f192ce
--- /dev/null
+++ b/testsuite/synth/issue937/ent.vhdl
@@ -0,0 +1,19 @@
+entity ent is
+    port (
+        i : in bit;
+        o : out bit
+    );
+end entity;
+
+architecture a of ent is
+    signal x : boolean;
+begin
+    process(i)
+    begin
+        if not x then
+            o <= i;
+        else
+            o <= '0';
+        end if;
+    end process;
+end;
diff --git a/testsuite/synth/issue937/tb_bnot.vhdl b/testsuite/synth/issue937/tb_bnot.vhdl
new file mode 100644
index 000000000..356b01d7c
--- /dev/null
+++ b/testsuite/synth/issue937/tb_bnot.vhdl
@@ -0,0 +1,23 @@
+entity tb_bnot is
+end tb_bnot;
+
+architecture behav of tb_bnot is
+  signal i : bit;
+  signal o : bit;
+begin
+  dut: entity work.bnot
+    port map (i, o);
+
+  process
+  begin
+    i <= '0';
+    wait for 1 ns;
+    assert o = '1' severity failure;
+
+    i <= '1';
+    wait for 1 ns;
+    assert o = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue937/tb_enot.vhdl b/testsuite/synth/issue937/tb_enot.vhdl
new file mode 100644
index 000000000..850a4b376
--- /dev/null
+++ b/testsuite/synth/issue937/tb_enot.vhdl
@@ -0,0 +1,31 @@
+entity tb_enot is
+end tb_enot;
+
+architecture behav of tb_enot is
+  signal i : bit;
+  signal x : boolean;
+  signal o : bit;
+begin
+  dut: entity work.enot
+    port map (i, x, o);
+
+  process
+  begin
+    i <= '0';
+    x <= false;
+    wait for 1 ns;
+    assert o = '0' severity failure;
+
+    i <= '1';
+    x <= false;
+    wait for 1 ns;
+    assert o = '1' severity failure;
+
+    i <= '1';
+    x <= True;
+    wait for 1 ns;
+    assert o = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue937/testsuite.sh b/testsuite/synth/issue937/testsuite.sh
new file mode 100755
index 000000000..24d93e2e8
--- /dev/null
+++ b/testsuite/synth/issue937/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in enot bnot; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"
-- 
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