From 28e8fd62c58280d96d4733418adc195e6f8db7b0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 21 Sep 2019 16:19:29 +0200
Subject: testsuite/synth: Add testcase for tgingold/ghdlsynth-beta#39

---
 testsuite/synth/issue39/rec.vhdl            | 43 -------------------
 testsuite/synth/issue39/record_test.vhdl    | 43 +++++++++++++++++++
 testsuite/synth/issue39/tb_record_test.vhdl | 65 +++++++++++++++++++++++++++++
 testsuite/synth/issue39/testsuite.sh        |  2 +-
 4 files changed, 109 insertions(+), 44 deletions(-)
 delete mode 100644 testsuite/synth/issue39/rec.vhdl
 create mode 100644 testsuite/synth/issue39/record_test.vhdl
 create mode 100644 testsuite/synth/issue39/tb_record_test.vhdl

(limited to 'testsuite')

diff --git a/testsuite/synth/issue39/rec.vhdl b/testsuite/synth/issue39/rec.vhdl
deleted file mode 100644
index b199cfa36..000000000
--- a/testsuite/synth/issue39/rec.vhdl
+++ /dev/null
@@ -1,43 +0,0 @@
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.numeric_std.all;
-
-entity record_test is
-  port (
-    clk : in std_logic;
-
-    sl_in : in std_logic;
-    slv_in : in std_logic_vector(7 downto 0);
-    int_in : in integer range 0 to 15;
-    usig_in : in unsigned(7 downto 0);
-
-    sl_out : out std_logic;
-    slv_out : out std_logic_vector(7 downto 0);
-    int_out : out integer range 0 to 15;
-    usig_out : out unsigned(7 downto 0)
-  );
-end record_test;
-
-architecture rtl of record_test is
-  type t_record is record
-    sl   : std_logic;
-    slv  : std_logic_vector(7 downto 0);
-    int  : integer range 0 to 15;
-    usig : unsigned(7 downto 0);
-  end record t_record;
-  signal sample_record : t_record := ('0', (others => '0'), 0, (others => '0'));
-begin
-  process(clk)
-  begin
-    if rising_edge(clk) then
-      sample_record.sl <= sl_in;
-      sample_record.slv <= slv_in;
-      sample_record.int <= int_in;
-      sample_record.usig <= usig_in;
-    end if;
-  end process;
-  sl_out <= sample_record.sl;
-  slv_out <= sample_record.slv;
-  int_out <= sample_record.int;
-  usig_out <= sample_record.usig;
-end rtl;
diff --git a/testsuite/synth/issue39/record_test.vhdl b/testsuite/synth/issue39/record_test.vhdl
new file mode 100644
index 000000000..b199cfa36
--- /dev/null
+++ b/testsuite/synth/issue39/record_test.vhdl
@@ -0,0 +1,43 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity record_test is
+  port (
+    clk : in std_logic;
+
+    sl_in : in std_logic;
+    slv_in : in std_logic_vector(7 downto 0);
+    int_in : in integer range 0 to 15;
+    usig_in : in unsigned(7 downto 0);
+
+    sl_out : out std_logic;
+    slv_out : out std_logic_vector(7 downto 0);
+    int_out : out integer range 0 to 15;
+    usig_out : out unsigned(7 downto 0)
+  );
+end record_test;
+
+architecture rtl of record_test is
+  type t_record is record
+    sl   : std_logic;
+    slv  : std_logic_vector(7 downto 0);
+    int  : integer range 0 to 15;
+    usig : unsigned(7 downto 0);
+  end record t_record;
+  signal sample_record : t_record := ('0', (others => '0'), 0, (others => '0'));
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      sample_record.sl <= sl_in;
+      sample_record.slv <= slv_in;
+      sample_record.int <= int_in;
+      sample_record.usig <= usig_in;
+    end if;
+  end process;
+  sl_out <= sample_record.sl;
+  slv_out <= sample_record.slv;
+  int_out <= sample_record.int;
+  usig_out <= sample_record.usig;
+end rtl;
diff --git a/testsuite/synth/issue39/tb_record_test.vhdl b/testsuite/synth/issue39/tb_record_test.vhdl
new file mode 100644
index 000000000..31db03d59
--- /dev/null
+++ b/testsuite/synth/issue39/tb_record_test.vhdl
@@ -0,0 +1,65 @@
+entity tb_record_test is
+end tb_record_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_record_test is
+  signal clk      : std_logic;
+  signal sl_in    : std_logic;
+  signal slv_in   : std_logic_vector(7 downto 0);
+  signal int_in   : integer range 0 to 15;
+  signal usig_in  : unsigned(7 downto 0);
+  signal sl_out   : std_logic;
+  signal slv_out  : std_logic_vector(7 downto 0);
+  signal int_out  : integer range 0 to 15;
+  signal usig_out : unsigned(7 downto 0);
+begin
+  dut: entity work.record_test
+    port map (
+      clk      => clk,
+      sl_in    => sl_in,
+      slv_in   => slv_in,
+      int_in   => int_in,
+      usig_in  => usig_in,
+      sl_out   => sl_out,
+      slv_out  => slv_out,
+      int_out  => int_out,
+      usig_out => usig_out);
+
+  process
+  begin
+    clk <= '0';
+    sl_in <= '1';
+    slv_in <= x"12";
+    int_in <= 13;
+    usig_in <= x"d5";
+
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+
+    assert sl_out = '1' severity failure;
+    assert slv_out = x"12" severity failure;
+    assert int_out = 13 severity failure;
+    assert usig_out = x"d5" severity failure;
+
+    sl_in <= '0';
+    slv_in <= x"9b";
+    int_in <= 3;
+    usig_in <= x"72";
+
+    clk <= '0';
+    wait for 1 ns;
+    clk <= '1';
+    wait for 1 ns;
+
+    assert sl_out = '0' severity failure;
+    assert slv_out = x"9b" severity failure;
+    assert int_out = 3 severity failure;
+    assert usig_out = x"72" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue39/testsuite.sh b/testsuite/synth/issue39/testsuite.sh
index b12533cc8..9bef83a1f 100755
--- a/testsuite/synth/issue39/testsuite.sh
+++ b/testsuite/synth/issue39/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in rec2; do
+for t in record_test rec2; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
cgit v1.2.3