From aff48727a4d0ad4058b7d43a86ebd6ed24b9cc6d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 12 Mar 2022 18:52:46 +0100
Subject: testsuite/synth: add test for #2002

---
 testsuite/synth/issue2002/bug.vhdl      | 14 ++++++++++++++
 testsuite/synth/issue2002/synth_bug.ref |  6 ++++++
 testsuite/synth/issue2002/testsuite.sh  |  8 ++++++++
 3 files changed, 28 insertions(+)
 create mode 100644 testsuite/synth/issue2002/bug.vhdl
 create mode 100644 testsuite/synth/issue2002/synth_bug.ref
 create mode 100755 testsuite/synth/issue2002/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue2002/bug.vhdl b/testsuite/synth/issue2002/bug.vhdl
new file mode 100644
index 000000000..176dcea0d
--- /dev/null
+++ b/testsuite/synth/issue2002/bug.vhdl
@@ -0,0 +1,14 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug is
+	port (
+		o : out std_ulogic_vector(33 downto 0)
+	);
+end bug;
+
+architecture struct of bug is
+    constant c : std_ulogic_vector(33 downto 0) := "0000000000000000000000000001111100";
+begin
+    o <= c;
+end architecture;
diff --git a/testsuite/synth/issue2002/synth_bug.ref b/testsuite/synth/issue2002/synth_bug.ref
new file mode 100644
index 000000000..3f74c866d
--- /dev/null
+++ b/testsuite/synth/issue2002/synth_bug.ref
@@ -0,0 +1,6 @@
+module bug
+  (output [33:0] o);
+  localparam [33:0] n1_o = 34'b0000000000000000000000000001111100;
+  assign o = n1_o;
+endmodule
+
diff --git a/testsuite/synth/issue2002/testsuite.sh b/testsuite/synth/issue2002/testsuite.sh
new file mode 100755
index 000000000..507fb72a3
--- /dev/null
+++ b/testsuite/synth/issue2002/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=verilog bug.vhdl -e > synth_bug.v
+diff_nocr synth_bug.ref synth_bug.v
+
+echo "Test successful"
-- 
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