From ace42254549d3d47cdb897e95c45cbb3ff966da0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 21 Sep 2019 09:32:36 +0200
Subject: testsuite/synth: add issue27 testcase.

---
 testsuite/synth/issue27/dff.vhdl     | 40 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/issue27/testsuite.sh |  8 ++++++++
 2 files changed, 48 insertions(+)
 create mode 100644 testsuite/synth/issue27/dff.vhdl
 create mode 100755 testsuite/synth/issue27/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue27/dff.vhdl b/testsuite/synth/issue27/dff.vhdl
new file mode 100644
index 000000000..2bf3ebec8
--- /dev/null
+++ b/testsuite/synth/issue27/dff.vhdl
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff is
+  generic(
+    formal_g : boolean := true
+  );
+  port(
+    reset : in std_logic;
+    clk : in std_logic;
+    d : in std_logic;
+    q : out std_logic
+  );
+end entity dff;
+
+architecture rtl of dff is
+  signal q_int : std_logic;
+begin
+
+  dff_proc : process(clk, reset)
+  begin
+    if reset = '1' then
+      q_int <= '0';
+    elsif rising_edge(clk) then
+      q_int <= d;
+    end if;
+  end process dff_proc;
+
+  -- drive q_int to output port
+  q <= q_int;
+
+  formal_gen : if formal_g = true generate
+  begin
+    -- set all declarations to run on clk
+    default clock is rising_edge(clk);
+    d_in_check : assert always {d} |=> {q_int};
+    not_d_in_check : assert always {not d} |=> {not q_int};
+  end generate formal_gen;
+
+end rtl;
diff --git a/testsuite/synth/issue27/testsuite.sh b/testsuite/synth/issue27/testsuite.sh
new file mode 100755
index 000000000..b5ed1a2b7
--- /dev/null
+++ b/testsuite/synth/issue27/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+synth dff.vhdl -e dff > syn_dff.vhdl
+
+echo "Test successful"
-- 
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