From 8a6f0ea2e97693dcefecfb29697f835729ead164 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 30 Jul 2019 20:56:54 +0200
Subject: synth: add a test for a ram.

---
 testsuite/synth/arr02/dpram1.vhdl    | 24 ++++++++++++++++++++++
 testsuite/synth/arr02/tb_dpram1.vhdl | 40 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/arr02/testsuite.sh   |  2 +-
 3 files changed, 65 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/arr02/dpram1.vhdl
 create mode 100644 testsuite/synth/arr02/tb_dpram1.vhdl

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/arr02/dpram1.vhdl b/testsuite/synth/arr02/dpram1.vhdl
new file mode 100644
index 000000000..ca1cf724a
--- /dev/null
+++ b/testsuite/synth/arr02/dpram1.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram1 is
+  port (raddr : std_logic_vector (3 downto 0);
+        rdat : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (3 downto 0);
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram1;
+
+architecture behav of dpram1 is
+  type memtype is array (15 downto 0) of std_logic_vector (7 downto 0);
+  signal mem : memtype;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      rdat <= mem (to_integer(unsigned (raddr)));
+      mem (to_integer(unsigned (waddr))) <= wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/tb_dpram1.vhdl b/testsuite/synth/arr02/tb_dpram1.vhdl
new file mode 100644
index 000000000..f7644fbfe
--- /dev/null
+++ b/testsuite/synth/arr02/tb_dpram1.vhdl
@@ -0,0 +1,40 @@
+entity tb_dpram1 is
+end tb_dpram1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram1 is
+  signal raddr : std_logic_vector(3 downto 0);
+  signal rdat : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(3 downto 0);
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram1
+    port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= "0000";
+    waddr <= "0001";
+    wdat <= x"01";
+    pulse;
+
+    raddr <= "0001";
+    waddr <= "0010";
+    wdat <= x"02";
+    pulse;
+    assert rdat = x"01" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/arr02/testsuite.sh b/testsuite/synth/arr02/testsuite.sh
index 75e5794a7..f11c3aa42 100755
--- a/testsuite/synth/arr02/testsuite.sh
+++ b/testsuite/synth/arr02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in rom1; do
+for t in rom1 dpram1; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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