From 8503d1a87282fdd57e7cd85007799ad752ebf048 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 16 Jan 2022 19:11:37 +0100
Subject: testsuite/synth: add a test for #1947

---
 testsuite/synth/issue1947/circuit.vhdl | 41 ++++++++++++++++++++++++++++++++++
 testsuite/synth/issue1947/testsuite.sh |  8 +++++++
 2 files changed, 49 insertions(+)
 create mode 100644 testsuite/synth/issue1947/circuit.vhdl
 create mode 100755 testsuite/synth/issue1947/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue1947/circuit.vhdl b/testsuite/synth/issue1947/circuit.vhdl
new file mode 100644
index 000000000..28aec7af0
--- /dev/null
+++ b/testsuite/synth/issue1947/circuit.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+package some_generic_package is
+    generic (
+        some_param : natural
+    );
+    procedure some_proc (
+        variable some_var : out std_logic
+    );
+end;
+package body some_generic_package is
+    procedure some_proc (
+        variable some_var : out std_logic
+    ) is
+    begin
+    end;
+end package body;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity circuit is
+    port (
+        clk : std_logic
+    );
+end;
+package package_instance is new work.some_generic_package
+    generic map(
+        4
+    );
+use work.package_instance.all;
+architecture rtl of circuit is
+begin
+    process
+        variable some_var : std_logic;
+    begin
+        wait until clk;
+
+        some_proc(some_var);
+
+    end process;
+end architecture;
diff --git a/testsuite/synth/issue1947/testsuite.sh b/testsuite/synth/issue1947/testsuite.sh
new file mode 100755
index 000000000..9cc452fc2
--- /dev/null
+++ b/testsuite/synth/issue1947/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only circuit
+
+echo "Test successful"
-- 
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