From 71cd14f43e9741a4a62a8dc3be6e3d55d3940db8 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 29 Jun 2019 18:43:12 +0200
Subject: testsuite: add synth/fsm01

---
 testsuite/synth/fsm01/fsm_4s.vhdl    | 46 ++++++++++++++++++++++++++++++++++++
 testsuite/synth/fsm01/tb_fsm_4s.vhdl | 44 ++++++++++++++++++++++++++++++++++
 testsuite/synth/fsm01/testsuite.sh   | 16 +++++++++++++
 3 files changed, 106 insertions(+)
 create mode 100644 testsuite/synth/fsm01/fsm_4s.vhdl
 create mode 100644 testsuite/synth/fsm01/tb_fsm_4s.vhdl
 create mode 100755 testsuite/synth/fsm01/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/fsm01/fsm_4s.vhdl b/testsuite/synth/fsm01/fsm_4s.vhdl
new file mode 100644
index 000000000..8403bc0b1
--- /dev/null
+++ b/testsuite/synth/fsm01/fsm_4s.vhdl
@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fsm_4s is
+  port (clk : std_logic;
+        rst : std_logic;
+        d : std_logic;
+        done : out std_logic);
+end fsm_4s;
+
+architecture behav of fsm_4s is
+  type state_t is (S0_1, S1_0, S2_0, S3_1);
+  signal s : state_t;
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        s <= S0_1;
+        done <= '0';
+      else
+        --  Reset by default
+        s <= S0_1;
+        done <= '0';
+        case s is
+          when S0_1 =>
+            if d = '1' then
+              s <= S1_0;
+            end if;
+          when S1_0 =>
+            if d = '0' then
+              s <= S2_0;
+            end if;
+          when S2_0 =>
+            if d = '0' then
+              s <= S3_1;
+            end if;
+          when S3_1 =>
+            if d = '1' then
+              done <= '1';
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/tb_fsm_4s.vhdl b/testsuite/synth/fsm01/tb_fsm_4s.vhdl
new file mode 100644
index 000000000..ecd6b9da0
--- /dev/null
+++ b/testsuite/synth/fsm01/tb_fsm_4s.vhdl
@@ -0,0 +1,44 @@
+entity tb_fsm_4s is
+end tb_fsm_4s;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_fsm_4s is
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal din : std_logic;
+  signal done : std_logic;
+begin
+  dut: entity work.fsm_4s
+    port map (
+      done => done,
+      d => din,
+      clk => clk,
+      rst => rst);
+
+  process
+    constant dat : std_logic_vector := b"1001_1001_1100";
+    constant res : std_logic_vector := b"0001_0001_0000";
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    din <= '0';
+    pulse;
+    assert done = '0' severity failure;
+    --  Test the whole sequence.
+    rst <= '0';
+    for i in dat'range loop
+      din <= dat (i);
+      pulse;
+      assert done = res(i) severity failure;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/fsm01/testsuite.sh b/testsuite/synth/fsm01/testsuite.sh
new file mode 100755
index 000000000..b9a451fa2
--- /dev/null
+++ b/testsuite/synth/fsm01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in fsm_4s; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"
-- 
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