From 6e51ccf3b2875a6b4e7ba1b7215b0ec28f0655b6 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 8 Aug 2019 05:28:17 +0200
Subject: synth: add testcase from #872

---
 testsuite/synth/issue872/alu.vhdl     | 42 +++++++++++++++++++++++++++++++++++
 testsuite/synth/issue872/testsuite.sh |  9 ++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 testsuite/synth/issue872/alu.vhdl
 create mode 100755 testsuite/synth/issue872/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue872/alu.vhdl b/testsuite/synth/issue872/alu.vhdl
new file mode 100644
index 000000000..19139792d
--- /dev/null
+++ b/testsuite/synth/issue872/alu.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity alu is
+  port (
+    clk : in std_logic;
+    rst : in std_logic;
+    opcode : in std_logic_vector(15 downto 0);
+    a : in std_logic;
+    b : in std_logic;
+    y : out std_logic
+  );
+end alu;
+
+architecture mux of alu is
+  signal ci : std_logic;
+  signal co : std_logic;
+  signal mux1, mux2: std_logic_vector(7 downto 0);
+begin
+
+  process(a, b, ci, mux1, mux2)
+    variable sel : unsigned(2 downto 0);
+  begin
+    sel := a & b & ci;
+    y <= mux1(to_integer(sel));
+    co <= mux2(to_integer(sel));
+  end process;
+
+  process(clk, rst)
+  begin
+    if(rst = '0') then
+      ci <= '0';
+      mux1 <= (others => '0');
+      mux2 <= (others => '0');
+    elsif(rising_edge(clk)) then
+      ci <= co;
+      mux1 <= opcode(15 downto 8);
+      mux2 <= opcode(7 downto 0);
+    end if;
+  end process;
+end mux;
diff --git a/testsuite/synth/issue872/testsuite.sh b/testsuite/synth/issue872/testsuite.sh
new file mode 100755
index 000000000..146289504
--- /dev/null
+++ b/testsuite/synth/issue872/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth alu.vhdl -e $t > syn_alu.vhdl
+analyze syn_alu.vhdl
+clean
+
+echo "Test successful"
-- 
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