From 163b5a804be113543276199ee36c193d7df75c8c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 7 Sep 2021 18:14:25 +0200
Subject: testsuite/synth: improve test for keep attribute

---
 testsuite/synth/synth154/err1.vhdl    | 48 +++++++++++++++++++++++++++++++++
 testsuite/synth/synth154/keep2.vhdl   | 50 +++++++++++++++++++++++++++++++++++
 testsuite/synth/synth154/testsuite.sh |  6 +++++
 3 files changed, 104 insertions(+)
 create mode 100644 testsuite/synth/synth154/err1.vhdl
 create mode 100644 testsuite/synth/synth154/keep2.vhdl

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/synth154/err1.vhdl b/testsuite/synth/synth154/err1.vhdl
new file mode 100644
index 000000000..f946a686b
--- /dev/null
+++ b/testsuite/synth/synth154/err1.vhdl
@@ -0,0 +1,48 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity leds is
+  port (clk : in std_logic;
+        led1, led2, led3, led4, led5 : out std_logic);
+end leds;
+
+architecture blink of leds is
+
+  signal clk_4hz: std_logic := '0';
+  constant gates: integer := 3 - 1;
+  constant max: integer := 3e6;
+  signal A: std_logic_vector(0 to gates) := ( others => '0');
+
+  signal B: std_logic := '1';
+  signal C: std_logic := '1';
+  signal val: std_logic := '0';
+  signal data: std_logic := '0';
+
+  attribute keep: string;
+  attribute keep of A: signal is "True ";
+begin
+  process (clk)
+    variable counter : unsigned (23 downto 0) := (others => '0');
+  begin
+    if rising_edge(clk) then
+      if counter >= max then
+        counter := x"000000";
+        clk_4hz <= not clk_4hz;
+      else
+        counter := counter + 1;
+      end if;
+    end if;
+  end process;
+
+GEN:
+    for i in 0 to gates generate
+        A(i) <= not A(gates - i);
+    end generate GEN;
+
+  led1 <= '0';
+  led2 <= clk_4hz;
+  led3 <= clk_4hz;
+  led4 <= clk_4hz;
+  led5 <= clk_4hz;
+end;
diff --git a/testsuite/synth/synth154/keep2.vhdl b/testsuite/synth/synth154/keep2.vhdl
new file mode 100644
index 000000000..504a33548
--- /dev/null
+++ b/testsuite/synth/synth154/keep2.vhdl
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity leds is
+  port (clk : in std_logic;
+        led1, led2, led3, led4, led5 : out std_logic);
+end leds;
+
+architecture blink of leds is
+
+  signal clk_4hz: std_logic := '0';
+  constant gates: integer := 3 - 1;
+  constant max: integer := 3e6;
+  signal A: std_logic_vector(0 to gates) := ( others => '0');
+
+  signal B: std_logic := '1';
+  signal C: std_logic := '1';
+  signal val: std_logic := '0';
+  signal data: std_logic := '0';
+
+  attribute keep: string;
+  attribute keep of A: signal is "true";
+  attribute keep of B: signal is "TRue";
+  attribute keep of C: signal is "false";
+begin
+  process (clk)
+    variable counter : unsigned (23 downto 0) := (others => '0');
+  begin
+    if rising_edge(clk) then
+      if counter >= max then
+        counter := x"000000";
+        clk_4hz <= not clk_4hz;
+      else
+        counter := counter + 1;
+      end if;
+    end if;
+  end process;
+
+GEN:
+    for i in 0 to gates generate
+        A(i) <= not A(gates - i);
+    end generate GEN;
+
+  led1 <= '0';
+  led2 <= clk_4hz;
+  led3 <= clk_4hz;
+  led4 <= clk_4hz;
+  led5 <= clk_4hz;
+end;
diff --git a/testsuite/synth/synth154/testsuite.sh b/testsuite/synth/synth154/testsuite.sh
index 00c001dcb..18f127b22 100755
--- a/testsuite/synth/synth154/testsuite.sh
+++ b/testsuite/synth/synth154/testsuite.sh
@@ -7,4 +7,10 @@ synth_analyze keep
 grep -q "signal a : " syn_keep.vhdl
 clean
 
+synth -Werror keep2.vhdl -e > syn_keep2.vhdl
+grep -q "signal a : " syn_keep2.vhdl
+clean
+
+synth_failure -Werror err1.vhdl -e
+
 echo "Test successful"
-- 
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