From 0e81b5f513517fff8b1c2043ada8f2b954f42e16 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 29 May 2020 18:44:06 +0200 Subject: testsuite/synth/subprg01: adjust test to avoid memory. --- testsuite/synth/subprg01/subprg02.vhdl | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'testsuite/synth/subprg01') diff --git a/testsuite/synth/subprg01/subprg02.vhdl b/testsuite/synth/subprg01/subprg02.vhdl index 76a2ba381..6939a1d1b 100644 --- a/testsuite/synth/subprg01/subprg02.vhdl +++ b/testsuite/synth/subprg01/subprg02.vhdl @@ -5,6 +5,7 @@ entity subprg02 is port (a : std_logic_vector (3 downto 0); n : natural range 0 to 1; clk : std_logic; + n0 : out std_logic_vector (3 downto 0); na : out std_logic_vector (3 downto 0)); end subprg02; @@ -24,5 +25,8 @@ begin neg (mem (n)); na <= mem (n); end if; + + -- FIXME: this is needed so that MEM is not considered as a memory. + n0 <= mem (0); end process; end behav; -- cgit v1.2.3