From 0416c788cd9aecd1a2bc8e7a517606d181d99921 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 28 Nov 2021 18:15:29 +0100 Subject: testsuite/synth: avoid use of verilog identifiers --- testsuite/synth/issue955/ent1.vhdl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'testsuite/synth/issue955') diff --git a/testsuite/synth/issue955/ent1.vhdl b/testsuite/synth/issue955/ent1.vhdl index 68c0f9c06..0e4ff0697 100644 --- a/testsuite/synth/issue955/ent1.vhdl +++ b/testsuite/synth/issue955/ent1.vhdl @@ -11,15 +11,15 @@ end ent1; architecture a of ent1 is type reg_t is array(0 to 7) of std_logic_vector(0 to 7); - signal reg : reg_t := (x"10", x"11", x"12", x"13", + signal reg1 : reg_t := (x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17"); begin process(clk) begin if rising_edge(clk) then - reg <= reg(1 to 7) & x"00"; + reg1 <= reg1(1 to 7) & x"00"; end if; end process; - o <= reg (0); + o <= reg1 (0); end; -- cgit v1.2.3