From 6e9336d11dfc4f53dba234e1f02a2b0172461e0c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 25 Sep 2019 20:39:46 +0200 Subject: testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues. --- testsuite/synth/issue34/repro_rng1.vhdl | 42 --------------------------------- 1 file changed, 42 deletions(-) delete mode 100644 testsuite/synth/issue34/repro_rng1.vhdl (limited to 'testsuite/synth/issue34/repro_rng1.vhdl') diff --git a/testsuite/synth/issue34/repro_rng1.vhdl b/testsuite/synth/issue34/repro_rng1.vhdl deleted file mode 100644 index 9d5a70e04..000000000 --- a/testsuite/synth/issue34/repro_rng1.vhdl +++ /dev/null @@ -1,42 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity sub_rng1 is - port ( - clk : in std_logic; - a : in natural range 0 to 7; - b : out natural range 0 to 7 - ); -end sub_rng1; - -architecture rtl of sub_rng1 is -begin - process(clk) - begin - if rising_edge(clk) then - b <= a; - end if; - end process; -end rtl; - - -library ieee; -use ieee.std_logic_1164.all; - -entity repro_rng1 is - port ( - clk : in std_logic; - a : in natural range 0 to 7; - b : out natural range 0 to 7 - ); -end repro_rng1; - -architecture rtl of repro_rng1 is -begin - i_sub_rng1 : entity work.sub_rng1 - port map ( - clk => clk, - a => a, - b => b - ); -end rtl; -- cgit v1.2.3