From e760a611da905b740f50ab02a58ed6b845e78af3 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 3 Feb 2023 19:11:42 +0100
Subject: testsuite/synth: add a test for #2336

---
 testsuite/synth/issue2336/top_ecp5pll.vhd | 51 +++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 testsuite/synth/issue2336/top_ecp5pll.vhd

(limited to 'testsuite/synth/issue2336/top_ecp5pll.vhd')

diff --git a/testsuite/synth/issue2336/top_ecp5pll.vhd b/testsuite/synth/issue2336/top_ecp5pll.vhd
new file mode 100644
index 000000000..a64aa187c
--- /dev/null
+++ b/testsuite/synth/issue2336/top_ecp5pll.vhd
@@ -0,0 +1,51 @@
+-- (c)EMARD
+-- License=BSD
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity top_ecp5pll is
+  generic
+  (
+    bits: integer := 26
+  );
+  port
+  (
+    clk_25mhz : in  std_logic;  -- main clock input from 25MHz clock source
+    led       : out std_logic_vector(7 downto 0)
+  );
+end;
+
+architecture mix of top_ecp5pll is
+    type T_blink is array (0 to 3) of unsigned(bits-1 downto 0);
+    signal R_blink: T_blink;
+    signal clocks: std_logic_vector(3 downto 0);
+begin
+    clkgen_inst: entity work.ecp5pll
+    generic map
+    (
+        in_Hz => natural( 25.0e6),
+      out0_Hz => natural( 40.0e6),                  out0_tol_hz => 0,
+      out1_Hz => natural( 50.0e6), out1_deg =>  90, out1_tol_hz => 0,
+      out2_Hz => natural( 60.0e6), out2_deg => 180, out2_tol_hz => 0,
+      out3_Hz => natural(  6.0e6), out3_deg => 300, out3_tol_hz => 10
+    )
+    port map
+    (
+      clk_i => clk_25mhz,
+      clk_o => clocks
+    );
+
+    G_blinks: for i in 0 to 3
+    generate
+      process(clocks(i))
+      begin
+        if rising_edge(clocks(i)) then
+          R_blink(i) <= R_blink(i)+1;
+        end if;
+        led(2*i+1 downto 2*i) <= std_logic_vector(R_blink(i)(bits-1 downto bits-2));
+      end process;
+    end generate;
+
+end mix;
-- 
cgit v1.2.3