From 1f74b9c76a10dc727531996a134a933a242c022e Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 13 Mar 2021 07:56:16 +0100 Subject: testsuite/synth: add a test for #1681 --- testsuite/synth/issue1681/repro3.vhdl | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 testsuite/synth/issue1681/repro3.vhdl (limited to 'testsuite/synth/issue1681/repro3.vhdl') diff --git a/testsuite/synth/issue1681/repro3.vhdl b/testsuite/synth/issue1681/repro3.vhdl new file mode 100644 index 000000000..b93cb9609 --- /dev/null +++ b/testsuite/synth/issue1681/repro3.vhdl @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro3 is + generic( + clock_count_c : natural range 1 to 2 := 2 + ); + port( + reset_n_i : in std_ulogic; + clock_i : in std_ulogic_vector(0 to clock_count_c-1) + ); + +end ; + +architecture beh of repro3 is + + type regs_t is + record + foo: std_ulogic; + end record; + + signal r, rin: regs_t; + +begin + + regs: process (clock_i, reset_n_i) + begin + if clock_i(clock_count_c-1)'event and clock_i(1) = '1' then + if reset_n_i = '0' then + r.foo <= '0'; + else + r <= rin; + end if; + end if; + end process; + +end architecture; -- cgit v1.2.3