From 1f5e5aa9a53c333a4e3576a52a128b38860d1f5b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 5 Sep 2020 07:51:53 +0200
Subject: testsuite/synth: add a test for #1454

---
 testsuite/synth/issue1454/dummy_top.vhdl     | 45 +++++++++++++++++++++++++++
 testsuite/synth/issue1454/dummy_top2.vhdl    | 46 ++++++++++++++++++++++++++++
 testsuite/synth/issue1454/tb_dummy_top.vhdl  | 24 +++++++++++++++
 testsuite/synth/issue1454/tb_dummy_top2.vhdl | 24 +++++++++++++++
 testsuite/synth/issue1454/testsuite.sh       | 10 ++++++
 5 files changed, 149 insertions(+)
 create mode 100644 testsuite/synth/issue1454/dummy_top.vhdl
 create mode 100644 testsuite/synth/issue1454/dummy_top2.vhdl
 create mode 100644 testsuite/synth/issue1454/tb_dummy_top.vhdl
 create mode 100644 testsuite/synth/issue1454/tb_dummy_top2.vhdl
 create mode 100755 testsuite/synth/issue1454/testsuite.sh

(limited to 'testsuite/synth/issue1454')

diff --git a/testsuite/synth/issue1454/dummy_top.vhdl b/testsuite/synth/issue1454/dummy_top.vhdl
new file mode 100644
index 000000000..5d0733355
--- /dev/null
+++ b/testsuite/synth/issue1454/dummy_top.vhdl
@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity dummy_sub is
+port (
+  clk : in std_logic;
+  dummy : out std_logic
+);
+end entity;
+
+
+architecture a of dummy_sub is
+  signal first_cycle : std_logic := '1';
+begin
+  support : process
+  begin
+    wait until rising_edge(clk);
+    dummy <= '0';
+    assert clk = '0';
+  end process;
+  
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dummy_top is
+  port(
+    clk : in std_logic;
+    dummy : out std_logic
+  );
+end entity;
+
+architecture a of dummy_top is
+begin
+  ------------------------------------------------------------------------------
+  dummy_sub_inst : entity work.dummy_sub
+    port map(
+      clk => clk,
+      dummy => open -- Connecting dummy here triggers instantiation of dummy_sub
+    );
+
+end architecture;
diff --git a/testsuite/synth/issue1454/dummy_top2.vhdl b/testsuite/synth/issue1454/dummy_top2.vhdl
new file mode 100644
index 000000000..7b110a058
--- /dev/null
+++ b/testsuite/synth/issue1454/dummy_top2.vhdl
@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity dummy_sub2 is
+port (
+  clk : in std_logic;
+  dummy : out std_logic
+);
+end entity;
+
+
+architecture a of dummy_sub2 is
+  signal first_cycle : std_logic := '1';
+begin
+  support : process (clk)
+  begin
+    if rising_edge(clk) then
+      dummy <= '0';
+      assert clk = '0';
+    end if;
+  end process;
+  
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dummy_top2 is
+  port(
+    clk : in std_logic;
+    dummy : out std_logic
+  );
+end entity;
+
+architecture a of dummy_top2 is
+begin
+  ------------------------------------------------------------------------------
+  dummy_sub_inst : entity work.dummy_sub2
+    port map(
+      clk => clk,
+      dummy => open -- Connecting dummy here triggers instantiation of dummy_sub
+    );
+
+end architecture;
diff --git a/testsuite/synth/issue1454/tb_dummy_top.vhdl b/testsuite/synth/issue1454/tb_dummy_top.vhdl
new file mode 100644
index 000000000..8aff91f8f
--- /dev/null
+++ b/testsuite/synth/issue1454/tb_dummy_top.vhdl
@@ -0,0 +1,24 @@
+entity tb_dummy_top is
+end tb_dummy_top;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dummy_top is
+  signal clk : std_logic;
+  signal d : std_logic;
+begin
+  dut: entity work.dummy_top
+    port map (clk, d);
+
+  process
+  begin
+    for i in 1 to 4 loop
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1454/tb_dummy_top2.vhdl b/testsuite/synth/issue1454/tb_dummy_top2.vhdl
new file mode 100644
index 000000000..2d597fc77
--- /dev/null
+++ b/testsuite/synth/issue1454/tb_dummy_top2.vhdl
@@ -0,0 +1,24 @@
+entity tb_dummy_top2 is
+end tb_dummy_top2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dummy_top2 is
+  signal clk : std_logic;
+  signal d : std_logic;
+begin
+  dut: entity work.dummy_top2
+    port map (clk, d);
+
+  process
+  begin
+    for i in 1 to 4 loop
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1454/testsuite.sh b/testsuite/synth/issue1454/testsuite.sh
new file mode 100755
index 000000000..37bda185b
--- /dev/null
+++ b/testsuite/synth/issue1454/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze dummy_top
+grep -q dummy_sub_inst syn_dummy_top.vhdl
+
+clean
+
+echo "Test successful"
-- 
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