From 05c630e2308f3d03cf741785a6cdc1f4258ab5e3 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 19 Jan 2020 04:31:17 +0100
Subject: testsuite/synth: add test for #1099

---
 testsuite/synth/issue1099/testsuite.sh |  7 +++++++
 testsuite/synth/issue1099/top.vhdl     | 36 ++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100755 testsuite/synth/issue1099/testsuite.sh
 create mode 100644 testsuite/synth/issue1099/top.vhdl

(limited to 'testsuite/synth/issue1099')

diff --git a/testsuite/synth/issue1099/testsuite.sh b/testsuite/synth/issue1099/testsuite.sh
new file mode 100755
index 000000000..19e77b72f
--- /dev/null
+++ b/testsuite/synth/issue1099/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth top.vhdl -e > syn_top.vhdl
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1099/top.vhdl b/testsuite/synth/issue1099/top.vhdl
new file mode 100644
index 000000000..99fa724e5
--- /dev/null
+++ b/testsuite/synth/issue1099/top.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity has_zero_width_port is
+  port(
+    width_one_port: out std_logic_vector(0 downto 0);
+    width_zero_port: out std_logic_vector(-1 downto 0)
+    );
+end entity;
+
+architecture arch of has_zero_width_port is
+begin
+  width_one_port <= (others => '0');
+  width_zero_port <= (others => '0');
+end architecture;
+    
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top is
+  port(
+    width_one_port: out std_logic_vector(0 downto 0);
+    width_zero_port: out std_logic_vector(-1 downto 0)
+    );
+end entity;
+
+architecture arch of top is
+begin
+
+  wrapped: entity work.has_zero_width_port
+    port map (
+      width_one_port => width_one_port,
+      width_zero_port => width_zero_port
+      );
+
+end architecture;
-- 
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