From 20da7909751eb191e6c77bed5fc5b6bc0d7374f1 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 8 Oct 2019 06:29:20 +0200
Subject: testsuite/synth: add a test.

---
 testsuite/synth/dff02/dff06.vhdl | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 testsuite/synth/dff02/dff06.vhdl

(limited to 'testsuite/synth/dff02/dff06.vhdl')

diff --git a/testsuite/synth/dff02/dff06.vhdl b/testsuite/synth/dff02/dff06.vhdl
new file mode 100644
index 000000000..a8cad2c04
--- /dev/null
+++ b/testsuite/synth/dff02/dff06.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff06 is
+  port (q : out std_logic_vector(7 downto 0);
+        d : std_logic_vector(7 downto 0);
+        clk : std_logic;
+        rst : std_logic);
+end dff06;
+
+architecture behav of dff06 is
+  signal p : std_logic_vector(7 downto 0);
+begin
+  process (clk, rst) is
+  begin
+    if rst = '1' then
+      p <= x"00";
+    elsif rising_edge (clk) then
+      q <= d;
+    end if;
+  end process;
+end behav;
-- 
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