From 9a183c7b6af43d741c77e419f33ed8e5d48001d1 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 19 May 2019 18:53:40 +0200 Subject: dff01: add more tests. --- testsuite/synth/dff01/dff06.vhdl | 21 +++++++++++++++++++++ testsuite/synth/dff01/dff07.vhdl | 21 +++++++++++++++++++++ testsuite/synth/dff01/testsuite.sh | 2 ++ 3 files changed, 44 insertions(+) create mode 100644 testsuite/synth/dff01/dff06.vhdl create mode 100644 testsuite/synth/dff01/dff07.vhdl (limited to 'testsuite/synth/dff01') diff --git a/testsuite/synth/dff01/dff06.vhdl b/testsuite/synth/dff01/dff06.vhdl new file mode 100644 index 000000000..33f5590a6 --- /dev/null +++ b/testsuite/synth/dff01/dff06.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff06 is + port (q : out std_logic; + d : std_logic; + clk : std_logic); +end dff06; + +architecture behav of dff06 is +begin + process (clk) is + variable a, b : std_logic; + begin + if rising_edge (clk) then + q <= b; + b := a; + a := d; + end if; + end process; +end behav; diff --git a/testsuite/synth/dff01/dff07.vhdl b/testsuite/synth/dff01/dff07.vhdl new file mode 100644 index 000000000..a90bbc8ab --- /dev/null +++ b/testsuite/synth/dff01/dff07.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff07 is + port (q : out std_logic; + d : std_logic; + clk : std_logic); +end dff07; + +architecture behav of dff07 is +begin + process (clk) is + variable a, b : std_logic; + begin + if rising_edge (clk) then + a := d; + b := a; + q <= b; + end if; + end process; +end behav; diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh index 12c11db33..dc50aa0ff 100755 --- a/testsuite/synth/dff01/testsuite.sh +++ b/testsuite/synth/dff01/testsuite.sh @@ -7,6 +7,8 @@ synth dff02.vhdl -e dff02 synth dff03.vhdl -e dff03 synth dff04.vhdl -e dff04 synth dff05.vhdl -e dff05 +synth dff06.vhdl -e dff06 +synth dff07.vhdl -e dff07 clean -- cgit v1.2.3