From 5e5e2fb50ed6eba32d614c9c566e280a6f992acb Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 22 Dec 2022 23:14:54 +0100 Subject: Changed doc comment position. --- testsuite/pyunit/dom/examples/SimpleEntity.vhdl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'testsuite/pyunit') diff --git a/testsuite/pyunit/dom/examples/SimpleEntity.vhdl b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl index bdeae47e1..8acc3ddb5 100644 --- a/testsuite/pyunit/dom/examples/SimpleEntity.vhdl +++ b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl @@ -35,8 +35,10 @@ entity Counter is end entity; --- Synthesizable and simulatable variant of a generic counter. architecture rtl of Counter is + -- Synthesizable and simulatable variant of a generic counter. + + -- Internal counter value signal CounterValue : unsigned(log2(MODULO) - 1 downto 0) := (others => '0'); begin process (Clock) -- cgit v1.2.3