From 301dea333ec3e28e95a43b1a4af569ebbedd6ab9 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 30 Jun 2021 13:52:30 +0200 Subject: Added package declarations inside of declarations. Added PSL Default clock (dummy). Added Disconnect specification (dummy). --- testsuite/pyunit/Current.vhdl | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'testsuite/pyunit/Current.vhdl') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index b2c7aff11..93474000b 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -77,6 +77,13 @@ architecture behav of entity_1 is attribute att : boolean; alias bar is boolean; + + disconnect address_bus : resolved_word after 3 ns; + disconnect others : resolved_word after 2 ns; + + default clock is rising_edge(clk); + package inner_pack is + end package; begin process(Clock) begin @@ -100,7 +107,7 @@ package package_1 is type cell; constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3; - attribute fixed of ghdl [bar] : constant is true; + attribute fixed of ghdl, gtkwave [x, y] : constant is true; component comp is port ( -- cgit v1.2.3