From f53677c01460f1d707ddc10d2bac9872b520460e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 27 Jun 2017 20:02:10 +0200
Subject: Add testcase for #373

---
 testsuite/gna/issue373/e.vhdl       | 20 ++++++++++++++++++++
 testsuite/gna/issue373/testsuite.sh | 10 ++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 testsuite/gna/issue373/e.vhdl
 create mode 100755 testsuite/gna/issue373/testsuite.sh

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue373/e.vhdl b/testsuite/gna/issue373/e.vhdl
new file mode 100644
index 000000000..395e8c6e9
--- /dev/null
+++ b/testsuite/gna/issue373/e.vhdl
@@ -0,0 +1,20 @@
+entity x is
+  port(
+    t :out bit_vector(0 to 0);
+    z :out bit_vector(0 to 0)
+  );
+end entity;
+architecture a of x is begin end architecture;
+
+entity e is end entity;
+architecture a of e is
+  constant z :integer := 0;
+  subtype t is bit_vector(0 to 0);
+  signal actual_for_t :bit;
+  signal actual_for_z :t;
+begin
+  inst: entity work.x port map(
+    t(z) => actual_for_t,
+    t(z) => actual_for_z
+  );
+end architecture;
diff --git a/testsuite/gna/issue373/testsuite.sh b/testsuite/gna/issue373/testsuite.sh
new file mode 100755
index 000000000..57536e34f
--- /dev/null
+++ b/testsuite/gna/issue373/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze e.vhdl
+elab_simulate e
+
+clean
+
+echo "Test successful"
-- 
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