From 5a97d9f219e116bd62b64294dc3d95678b3415f8 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 27 Oct 2018 08:55:47 +0200
Subject: Add testcase for #679

---
 testsuite/gna/issue679/repro.vhdl   | 14 ++++++++++++++
 testsuite/gna/issue679/testsuite.sh |  9 +++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 testsuite/gna/issue679/repro.vhdl
 create mode 100755 testsuite/gna/issue679/testsuite.sh

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue679/repro.vhdl b/testsuite/gna/issue679/repro.vhdl
new file mode 100644
index 000000000..2aa5e63df
--- /dev/null
+++ b/testsuite/gna/issue679/repro.vhdl
@@ -0,0 +1,14 @@
+entity repro is
+end repro;
+
+architecture behav of repro is
+   signal clk : bit;
+   signal cyc: bit;
+   signal wen : bit;
+   signal lw : bit;
+begin
+   -- psl default clock is clk;
+
+   -- psl c1: assert always lw -> cyc and (next not(wen))
+   --  report "error";
+end;
diff --git a/testsuite/gna/issue679/testsuite.sh b/testsuite/gna/issue679/testsuite.sh
new file mode 100755
index 000000000..d44aa19d3
--- /dev/null
+++ b/testsuite/gna/issue679/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze -fpsl repro.vhdl
+
+clean
+
+echo "Test successful"
-- 
cgit v1.2.3