From 46813f4ed4010b27ce83b8b35d866539de6746a2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 2 Jan 2019 08:35:46 +0100
Subject: Add testcase #339.

Close #339
---
 testsuite/gna/issue339/test_bench.vhdl | 40 ++++++++++++++++++++++++++++++++++
 testsuite/gna/issue339/test_pkg.vhdl   | 22 +++++++++++++++++++
 testsuite/gna/issue339/testsuite.sh    | 11 ++++++++++
 3 files changed, 73 insertions(+)
 create mode 100644 testsuite/gna/issue339/test_bench.vhdl
 create mode 100644 testsuite/gna/issue339/test_pkg.vhdl
 create mode 100755 testsuite/gna/issue339/testsuite.sh

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue339/test_bench.vhdl b/testsuite/gna/issue339/test_bench.vhdl
new file mode 100644
index 000000000..74344dac7
--- /dev/null
+++ b/testsuite/gna/issue339/test_bench.vhdl
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.fixed_pkg.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+library work;
+use work.test_pkg.all;
+
+
+entity test_bench is
+
+end entity;
+
+
+architecture bench of test_bench is
+    signal counter    : natural range 0 to 1000;
+    signal my_signal  : sfixed(0 downto -15);
+    signal my_array   : t_sf_array(0 to 15)(0 downto -15) := do_something(16, my_signal);
+    signal s_rst      : std_logic := '1'; 
+    signal s_clk      : std_logic := '1';
+
+begin
+    s_rst <= '1' after 50 ns;
+    s_clk <= not s_clk after 10 ns;
+
+    write_result : process (s_rst, s_clk) is
+        file test_file   : text open write_mode is "output.txt";
+        variable wrline  : line;
+        variable linenum : integer := 0;
+    begin
+        if (s_rst = '1') then
+            linenum := 0;
+        elsif (rising_edge(s_clk) and counter < 16) then
+            write(wrline, real'image(to_real(my_array(counter))));
+            writeline(test_file, wrline);
+        end if;
+    end process;
+end architecture;
diff --git a/testsuite/gna/issue339/test_pkg.vhdl b/testsuite/gna/issue339/test_pkg.vhdl
new file mode 100644
index 000000000..1036fa52d
--- /dev/null
+++ b/testsuite/gna/issue339/test_pkg.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.fixed_pkg.all;
+
+package test_pkg is
+    type t_sf_array is array (natural range <>) of sfixed;
+    impure function do_something(samples : integer; ret_type : sfixed) return t_sf_array;
+end package;
+
+package body test_pkg is
+    impure function do_something(samples : integer; ret_type : sfixed) return t_sf_array is
+        variable init_array      : t_sf_array(0 to samples - 1)(ret_type'left downto ret_type'right) := (others => (others => '0'));
+
+    begin
+        for i in 0 to (samples - 1) loop
+            init_array(i)   := to_sfixed(1.0/real(1+i), ret_type);
+        end loop;
+        return init_array;
+    end function;
+
+end package body;
diff --git a/testsuite/gna/issue339/testsuite.sh b/testsuite/gna/issue339/testsuite.sh
new file mode 100755
index 000000000..8d02ad161
--- /dev/null
+++ b/testsuite/gna/issue339/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test_pkg.vhdl test_bench.vhdl
+elab_simulate test_bench --stop-time=700ns
+
+clean
+
+echo "Test successful"
-- 
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