From 429e36bf14976d2bb3f173cbc99c204ac3a5994a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 15 Mar 2019 14:01:42 +0100 Subject: Add testcase for #736 --- testsuite/gna/issue736/repro.vhdl | 31 +++++++++++ testsuite/gna/issue736/simple_fsm.vhdl | 46 ++++++++++++++++ testsuite/gna/issue736/tb_simple_fsm.vhdl | 92 +++++++++++++++++++++++++++++++ testsuite/gna/issue736/testsuite.sh | 14 +++++ 4 files changed, 183 insertions(+) create mode 100644 testsuite/gna/issue736/repro.vhdl create mode 100644 testsuite/gna/issue736/simple_fsm.vhdl create mode 100644 testsuite/gna/issue736/tb_simple_fsm.vhdl create mode 100755 testsuite/gna/issue736/testsuite.sh (limited to 'testsuite/gna') diff --git a/testsuite/gna/issue736/repro.vhdl b/testsuite/gna/issue736/repro.vhdl new file mode 100644 index 000000000..3ac0b65d5 --- /dev/null +++ b/testsuite/gna/issue736/repro.vhdl @@ -0,0 +1,31 @@ +entity repro is +end repro; + +architecture behav of repro is + signal a, i, r : bit; +begin + process (all) + begin + r <= a when i = '0' else not a; + end process; + + process + begin + i <= '0'; + a <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + i <= '0'; + a <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + i <= '1'; + a <= '1'; + wait for 1 ns; + assert r = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/gna/issue736/simple_fsm.vhdl b/testsuite/gna/issue736/simple_fsm.vhdl new file mode 100644 index 000000000..dfc871ba9 --- /dev/null +++ b/testsuite/gna/issue736/simple_fsm.vhdl @@ -0,0 +1,46 @@ +--Standard Library +library ieee; +--Standard Packages +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity simple_fsm is + port ( + clk : in std_logic; + rst : in std_logic; + + valid : in std_logic; + invalid : in std_logic + ); +end simple_fsm; + +architecture rtl of simple_fsm is + + type t_states is (e_IDLE, e_S1); + signal p_state : t_states := e_IDLE; + signal n_state : t_states; + +begin + + p_sync_fsm : process(clk) + begin + if rising_edge(clk) then + if (rst = '1') then + p_state <= e_IDLE; + else + p_state <= n_state; + end if; + end if; + end process; + + p_comb_fsm : process (all) + begin + case p_state is + when e_IDLE => + n_state <= e_S1 when valid = '1' else e_IDLE; + when e_S1 => + n_state <= e_IDLE when (valid = '0' and invalid = '1') else e_S1; + end case; + end process; + +end rtl; diff --git a/testsuite/gna/issue736/tb_simple_fsm.vhdl b/testsuite/gna/issue736/tb_simple_fsm.vhdl new file mode 100644 index 000000000..6db54a67e --- /dev/null +++ b/testsuite/gna/issue736/tb_simple_fsm.vhdl @@ -0,0 +1,92 @@ +--Standard Library +library ieee; +--Standard Packages +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_simple_fsm is +end tb_simple_fsm; + +architecture tb of tb_simple_fsm is + + signal clk : std_logic := '0'; + signal rst : std_logic := '0'; + signal valid : std_logic := '0'; + signal invalid : std_logic := '0'; + + + -- Simulation support + signal clock_ena : boolean := false; + constant C_CLK_PERIOD : time := 10 ns; + +------------------------------------------------------------------------------- +-- Clock generator procedure +------------------------------------------------------------------------------- + procedure clock_gen( + signal clock_signal : inout std_logic; + signal clock_ena : in boolean; + constant clock_period : in time + ) is + variable v_first_half_clk_period : time := clock_period / 2; + begin + loop + if not clock_ena then + wait until clock_ena; + end if; + wait for v_first_half_clk_period; + clock_signal <= not clock_signal; + wait for (clock_period - v_first_half_clk_period); + clock_signal <= not clock_signal; + end loop; + end; + + +begin + + clock_gen(clk, clock_ena, C_CLK_PERIOD); + + ----------------------------------------------------------------------------- + -- DUT + ----------------------------------------------------------------------------- + dut : entity work.simple_fsm + port map ( + clk => clk, + rst => rst, + valid => valid, + invalid => invalid); + + p_main : process + begin + wait for 100 ns; + rst <= '1'; + wait for 100 ns; + clock_ena <= true; + wait for 100 ns; + valid <= '1'; + wait for 100 ns; + valid <= '0'; + wait for 100 ns; + invalid <= '1'; + wait for 100 ns; + invalid <= '0'; + wait for 100 ns; + + + rst <= '0'; + + wait for 100 ns; + valid <= '1'; + wait for 100 ns; + valid <= '0'; + wait for 100 ns; + invalid <= '1'; + wait for 100 ns; + invalid <= '0'; + wait for 100 ns; + + -- end sim + clock_ena <= false; + wait; + + end process; +end tb; diff --git a/testsuite/gna/issue736/testsuite.sh b/testsuite/gna/issue736/testsuite.sh new file mode 100755 index 000000000..282eaffd1 --- /dev/null +++ b/testsuite/gna/issue736/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze simple_fsm.vhdl tb_simple_fsm.vhdl +elab_simulate tb_simple_fsm + +analyze repro.vhdl +elab_simulate repro + +clean + +echo "Test successful" -- cgit v1.2.3