From bffc53212d0bd2426cb39f5445c9c6b080508a2f Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 5 Sep 2019 21:43:22 +0200
Subject: testsuite: add testcase for #918

---
 testsuite/gna/issue918/ent.vhdl     | 44 +++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue918/testsuite.sh | 10 +++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 testsuite/gna/issue918/ent.vhdl
 create mode 100755 testsuite/gna/issue918/testsuite.sh

(limited to 'testsuite/gna/issue918')

diff --git a/testsuite/gna/issue918/ent.vhdl b/testsuite/gna/issue918/ent.vhdl
new file mode 100644
index 000000000..d030acff9
--- /dev/null
+++ b/testsuite/gna/issue918/ent.vhdl
@@ -0,0 +1,44 @@
+package power is
+  type voltage is range integer'low to integer'high units
+    uV;
+    mV = 1000 uV;
+     V = 1000 mV;
+    kV = 1000  V;
+  end units;
+end package;
+
+use work.power.all;
+
+entity LTC is
+  generic (
+    V_MIN : voltage := 0 V;
+    V_MAX : voltage := voltage'high
+  );
+  port (
+    Vin  : in  voltage range 0 V to 15 V;
+    Vout : out voltage range V_MIN to V_MAX
+  );
+end entity;
+
+architecture ic of LTC is
+begin
+  Vout <= Vin * 0.95;
+end architecture;
+
+use work.power.all;
+
+entity board is
+  port (
+    Vin  : in  voltage;
+    Vout : out voltage
+  );
+end entity;
+
+architecture ic of board is
+begin
+  U1: entity work.LTC
+    port map (
+      Vin  => 2.5 V,
+      Vout => open
+    );
+end architecture;
diff --git a/testsuite/gna/issue918/testsuite.sh b/testsuite/gna/issue918/testsuite.sh
new file mode 100755
index 000000000..1d15cd965
--- /dev/null
+++ b/testsuite/gna/issue918/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze ent.vhdl
+elab_simulate board
+
+clean
+
+echo "Test successful"
-- 
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