From 50da90f509aa6de2961f1795af0be2452bc2c6d9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 6 Feb 2019 20:23:52 +0100
Subject: Add testcase for #747

---
 testsuite/gna/issue747/fa.vhdl      | 17 +++++++++++
 testsuite/gna/issue747/fa_tb.vhdl   | 57 +++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue747/testsuite.sh | 11 +++++++
 3 files changed, 85 insertions(+)
 create mode 100644 testsuite/gna/issue747/fa.vhdl
 create mode 100644 testsuite/gna/issue747/fa_tb.vhdl
 create mode 100755 testsuite/gna/issue747/testsuite.sh

(limited to 'testsuite/gna/issue747')

diff --git a/testsuite/gna/issue747/fa.vhdl b/testsuite/gna/issue747/fa.vhdl
new file mode 100644
index 000000000..11530b709
--- /dev/null
+++ b/testsuite/gna/issue747/fa.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fa is
+  port(
+    a:in std_ulogic;
+    b: in std_ulogic;
+    ci: in std_ulogic;
+    co: out std_ulogic;
+    s: out std_ulogic);
+end fa;
+
+architecture fa_behave of fa is
+begin
+  s <= a xor b xor ci;
+  co <= (a and b) or (a and ci) or (b and ci);
+end fa_behave;
diff --git a/testsuite/gna/issue747/fa_tb.vhdl b/testsuite/gna/issue747/fa_tb.vhdl
new file mode 100644
index 000000000..600c02f47
--- /dev/null
+++ b/testsuite/gna/issue747/fa_tb.vhdl
@@ -0,0 +1,57 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fa_tb is
+end fa_tb;
+
+architecture fa_behave of fa_tb is
+  signal a, b, ci, co, s : std_ulogic;
+
+begin
+  DUT : entity work.fa
+    port map(a  => a,
+             b  => b,
+             ci => ci,
+             s  => s,
+             co => co);
+
+  process
+    type pattern_type is record
+      a, b, ci, s, co : std_ulogic;
+    end record;
+
+    type pattern_array is array (natural range <>) of pattern_type;
+    constant patterns : pattern_array :=
+      (('0', '0', '0', '0', '0'),
+       ('0', '0', '1', '1', '0'),
+       ('0', '1', '0', '1', '0'),
+       ('0', '1', '1', '0', '1'),
+       ('1', '0', '0', '1', '0'),
+       ('1', '0', '1', '0', '1'),
+       ('1', '1', '0', '0', '1'),
+       ('1', '1', '1', '1', '1'));
+
+  begin
+    for i in pattern_array'range loop
+      a  <= pattern_array(i).a;
+      b  <= pattern_array(i).b;
+      ci <= pattern_array(i).ci;
+
+      wait for 1 ns;
+      
+      assert s = pattern_array(i).s
+        report "bad sum value" severity error;
+
+      assert co = pattern_array(i).co
+        report "bad co value" severity error;
+
+    end loop;
+
+    assert false
+      report "end of test" severity note;
+
+    wait;
+  end process;
+
+end fa_behave;
+
diff --git a/testsuite/gna/issue747/testsuite.sh b/testsuite/gna/issue747/testsuite.sh
new file mode 100755
index 000000000..0f9f8991f
--- /dev/null
+++ b/testsuite/gna/issue747/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+#export GHDL_STD_FLAGS=--std=08
+analyze fa.vhdl
+analyze_failure fa_tb.vhdl
+
+clean
+
+echo "Test successful"
-- 
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