From 7c1a8746d2b4fc076bcb287c8917af750a6b3d58 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 8 Dec 2017 06:56:55 +0100
Subject: Add testcase for #478

---
 testsuite/gna/issue478/repro.vhdl   | 20 ++++++++++++++++++++
 testsuite/gna/issue478/repro2.vhdl  | 10 ++++++++++
 testsuite/gna/issue478/repro3.vhdl  | 10 ++++++++++
 testsuite/gna/issue478/repro4.vhdl  | 10 ++++++++++
 testsuite/gna/issue478/testsuite.sh | 12 ++++++++++++
 5 files changed, 62 insertions(+)
 create mode 100644 testsuite/gna/issue478/repro.vhdl
 create mode 100644 testsuite/gna/issue478/repro2.vhdl
 create mode 100644 testsuite/gna/issue478/repro3.vhdl
 create mode 100644 testsuite/gna/issue478/repro4.vhdl
 create mode 100755 testsuite/gna/issue478/testsuite.sh

(limited to 'testsuite/gna/issue478')

diff --git a/testsuite/gna/issue478/repro.vhdl b/testsuite/gna/issue478/repro.vhdl
new file mode 100644
index 000000000..e0a424ae7
--- /dev/null
+++ b/testsuite/gna/issue478/repro.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity EX_ALUControl is
+end entity;
+
+architecture foo of EX_ALUControl is
+    signal RST:             std_logic;
+    signal RDY:             std_logic;
+    signal reentry_guard:   std_logic;
+begin
+
+NO_LABEL:
+    process (RST, RDY, reentry_guard)
+    begin
+        report "In EX_ALUControl (RST=" & Std_logic'image(RST) & ", RDY=" & 
+        Std_logic'image(RDY) & ", re=" & 
+        Std_logic'image(reentry_guard) ")"; -- MISSING AMPERSAND
+    end process;
+end architecture;
diff --git a/testsuite/gna/issue478/repro2.vhdl b/testsuite/gna/issue478/repro2.vhdl
new file mode 100644
index 000000000..653fd283c
--- /dev/null
+++ b/testsuite/gna/issue478/repro2.vhdl
@@ -0,0 +1,10 @@
+entity repro2 is
+end;
+
+architecture behav of repro2 is
+begin
+   process
+   begin
+    "and";
+   end process;
+end;
diff --git a/testsuite/gna/issue478/repro3.vhdl b/testsuite/gna/issue478/repro3.vhdl
new file mode 100644
index 000000000..13e655902
--- /dev/null
+++ b/testsuite/gna/issue478/repro3.vhdl
@@ -0,0 +1,10 @@
+entity repro3 is
+end;
+
+architecture behav of repro3 is
+begin
+   process
+   begin
+    "and" (true, false);
+   end process;
+end;
diff --git a/testsuite/gna/issue478/repro4.vhdl b/testsuite/gna/issue478/repro4.vhdl
new file mode 100644
index 000000000..a32c72287
--- /dev/null
+++ b/testsuite/gna/issue478/repro4.vhdl
@@ -0,0 +1,10 @@
+entity repro4 is
+end;
+
+architecture behav of repro4 is
+begin
+   process
+   begin
+    "foo" (true, false);
+   end process;
+end;
diff --git a/testsuite/gna/issue478/testsuite.sh b/testsuite/gna/issue478/testsuite.sh
new file mode 100755
index 000000000..82f7efe59
--- /dev/null
+++ b/testsuite/gna/issue478/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure repro.vhdl
+analyze_failure repro2.vhdl
+analyze_failure repro3.vhdl
+analyze_failure repro4.vhdl
+
+clean
+
+echo "Test successful"
-- 
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