From a3e05191a62482c385ca5481caa78299fdbad775 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 3 Aug 2022 06:57:25 +0200
Subject: testsuite/gna: add a test for #2157

---
 testsuite/gna/issue2157/trepro.vhdl | 140 ++++++++++++++++++++++++++++++++++++
 1 file changed, 140 insertions(+)
 create mode 100644 testsuite/gna/issue2157/trepro.vhdl

(limited to 'testsuite/gna/issue2157/trepro.vhdl')

diff --git a/testsuite/gna/issue2157/trepro.vhdl b/testsuite/gna/issue2157/trepro.vhdl
new file mode 100644
index 000000000..9c0ddf2e1
--- /dev/null
+++ b/testsuite/gna/issue2157/trepro.vhdl
@@ -0,0 +1,140 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity sequencer is
+  generic (
+    seq : string
+  );
+  port (
+    clk  : in  std_logic;
+    data : out std_logic
+  );
+end entity sequencer;
+
+architecture rtl of sequencer is
+
+  signal index : natural := seq'low;
+
+  function to_bit (a : in character) return std_logic is
+    variable ret : std_logic;
+  begin
+    case a is
+      when '0' | '_' => ret := '0';
+      when '1' | '-' => ret := '1';
+      when others    => ret := 'X';
+    end case;
+    return ret;
+  end function to_bit;
+
+begin
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if (index < seq'high) then
+        index <= index + 1;
+      end if;
+    end if;
+  end process;
+
+  data <= to_bit(seq(index));
+
+end architecture rtl;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity hex_sequencer is
+  generic (
+    seq : string
+  );
+  port (
+    clk  : in  std_logic;
+    data : out std_logic_vector(3 downto 0)
+  );
+end entity hex_sequencer;
+
+architecture rtl of hex_sequencer is
+
+  signal index : natural := seq'low;
+
+  function to_hex (a : in character) return std_logic_vector is
+    variable ret : std_logic_vector(3 downto 0);
+  begin
+    case a is
+      when '0' | '_' => ret := x"0";
+      when '1'       => ret := x"1";
+      when '2'       => ret := x"2";
+      when '3'       => ret := x"3";
+      when '4'       => ret := x"4";
+      when '5'       => ret := x"5";
+      when '6'       => ret := x"6";
+      when '7'       => ret := x"7";
+      when '8'       => ret := x"8";
+      when '9'       => ret := x"9";
+      when 'a' | 'A' => ret := x"A";
+      when 'b' | 'B' => ret := x"B";
+      when 'c' | 'C' => ret := x"C";
+      when 'd' | 'D' => ret := x"D";
+      when 'e' | 'E' => ret := x"E";
+      when 'f' | 'F' | '-' => ret := x"F";
+      when others => ret := x"X";
+    end case;
+    return ret;
+  end function to_hex;
+
+begin
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if (index < seq'high) then
+        index <= index + 1;
+      end if;
+    end if;
+  end process;
+
+  data <= to_hex(seq(index));
+
+end architecture rtl;
+
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+entity issue is
+end entity issue;
+
+architecture psl of issue is
+
+  signal a, c : std_logic;
+  signal b : std_logic_vector(3 downto 0);
+
+  signal clk   : std_logic := '1';
+
+begin
+
+  --                                              012345678901234567892345
+  SEQ_A : entity work.sequencer generic map     ("_-______________-_______") port map (clk, a);
+  SEQ_B : entity work.hex_sequencer generic map ("443334477444433355555555") port map (clk, b);
+  SEQ_C : entity work.sequencer generic map     ("_____-___---______--_--_") port map (clk, c);
+
+
+  inst : entity work.repro
+    port map (a => a, b => b, c => c, clk => clk);
+
+  clk <= not clk after 500 ps;
+
+  -- stop simulation after 30 cycles
+  process
+    variable index : natural := 30;
+  begin
+    loop
+      wait until rising_edge(clk);
+      index := index - 1;
+      exit when index = 0;
+    end loop;
+    std.env.stop(0);
+  end process;
+end architecture psl;
-- 
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