From c3c11edfccd3fca36417ad2ad60531272c3766aa Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 16 Jan 2016 13:37:17 +0100
Subject: Add testcase for issue17.

---
 testsuite/gna/issue17/cond_assign_proc.vhdl | 30 ++++++++++++++++++++++++++++
 testsuite/gna/issue17/cond_assign_sig.vhdl  | 28 ++++++++++++++++++++++++++
 testsuite/gna/issue17/cond_assign_var.vhdl  | 31 +++++++++++++++++++++++++++++
 testsuite/gna/issue17/testsuite.sh          | 17 ++++++++++++++++
 4 files changed, 106 insertions(+)
 create mode 100644 testsuite/gna/issue17/cond_assign_proc.vhdl
 create mode 100644 testsuite/gna/issue17/cond_assign_sig.vhdl
 create mode 100644 testsuite/gna/issue17/cond_assign_var.vhdl
 create mode 100755 testsuite/gna/issue17/testsuite.sh

(limited to 'testsuite/gna/issue17')

diff --git a/testsuite/gna/issue17/cond_assign_proc.vhdl b/testsuite/gna/issue17/cond_assign_proc.vhdl
new file mode 100644
index 000000000..8a2660da8
--- /dev/null
+++ b/testsuite/gna/issue17/cond_assign_proc.vhdl
@@ -0,0 +1,30 @@
+library ieee ; 
+use ieee.std_logic_1164.all ; 
+use std.textio.all ; 
+
+entity cond_assign_proc is
+end entity cond_assign_proc ;
+architecture doit of cond_assign_proc is
+  signal Clk : std_logic := '0'  ; 
+  signal Y : std_logic ; 
+begin
+  Clk <= not Clk after 10 ns ; 
+  
+  process (Clk)
+    variable A : std_logic ; 
+  begin
+    A := 'H' when Clk = '1' else 'L' ;
+    Y <= A ; 
+--    Y <= 'H' when Clk = '1' else 'L' ;
+  end process ;
+
+--    Y <= 'H' when Clk = '1' else 'L' ;
+    
+  process
+  begin
+    wait for 500 ns ; 
+    std.env.stop ;
+  end process ; 
+end architecture doit ; 
+
+
diff --git a/testsuite/gna/issue17/cond_assign_sig.vhdl b/testsuite/gna/issue17/cond_assign_sig.vhdl
new file mode 100644
index 000000000..ad8a0a452
--- /dev/null
+++ b/testsuite/gna/issue17/cond_assign_sig.vhdl
@@ -0,0 +1,28 @@
+library ieee ; 
+use ieee.std_logic_1164.all ; 
+use std.textio.all ; 
+
+entity cond_assign_sig is
+end entity cond_assign_sig ;
+
+architecture doit of cond_assign_sig is
+  signal Clk : std_logic := '0'  ; 
+  signal Y : std_logic ; 
+begin
+  Clk <= not Clk after 10 ns ; 
+  
+  process (Clk)
+  begin
+    Y <= 'H' when Clk = '1' else 'L' ;
+  end process ;
+
+--    Y <= 'H' when Clk = '1' else 'L' ;
+    
+  process
+  begin
+    wait for 500 ns ; 
+    std.env.stop ;
+  end process ; 
+end architecture doit ; 
+
+
diff --git a/testsuite/gna/issue17/cond_assign_var.vhdl b/testsuite/gna/issue17/cond_assign_var.vhdl
new file mode 100644
index 000000000..c6e4af87f
--- /dev/null
+++ b/testsuite/gna/issue17/cond_assign_var.vhdl
@@ -0,0 +1,31 @@
+library ieee ; 
+use ieee.std_logic_1164.all ; 
+use std.textio.all ; 
+
+entity cond_assign_var is
+end entity cond_assign_var ;
+
+architecture doit of cond_assign_var is
+  signal Clk : std_logic := '0'  ; 
+  signal Y : std_logic ; 
+begin
+  Clk <= not Clk after 10 ns ; 
+  
+  process (Clk)
+    variable A : std_logic ; 
+  begin
+    A := 'H' when Clk = '1' else 'L' ;
+    Y <= A ; 
+--    Y <= 'H' when Clk = '1' else 'L' ;
+  end process ;
+
+--    Y <= 'H' when Clk = '1' else 'L' ;
+    
+  process
+  begin
+    wait for 500 ns ; 
+    std.env.stop ;
+  end process ; 
+end architecture doit ; 
+
+
diff --git a/testsuite/gna/issue17/testsuite.sh b/testsuite/gna/issue17/testsuite.sh
new file mode 100755
index 000000000..d5b08e918
--- /dev/null
+++ b/testsuite/gna/issue17/testsuite.sh
@@ -0,0 +1,17 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+analyze cond_assign_var.vhdl
+elab_simulate cond_assign_var
+
+analyze cond_assign_sig.vhdl
+elab_simulate cond_assign_sig
+
+analyze cond_assign_proc.vhdl
+elab_simulate cond_assign_proc
+
+clean
+
+echo "Test successful"
-- 
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