From b7a72ac6b84fca5fdd84a0656b87ad25a643c1f0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 5 Dec 2016 03:20:42 +0100
Subject: Add testcase for #151

---
 testsuite/gna/issue151/tb.vhdl      | 19 +++++++++++++++++++
 testsuite/gna/issue151/testsuite.sh |  8 ++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 testsuite/gna/issue151/tb.vhdl
 create mode 100755 testsuite/gna/issue151/testsuite.sh

(limited to 'testsuite/gna/issue151')

diff --git a/testsuite/gna/issue151/tb.vhdl b/testsuite/gna/issue151/tb.vhdl
new file mode 100644
index 000000000..8aadd3f4b
--- /dev/null
+++ b/testsuite/gna/issue151/tb.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+ port (in_vec   : in std_logic_vector);
+end entity;
+
+architecture rtl of test is
+signal A : natural;
+begin
+
+  gen2 : if in_vec'length <= 2 generate
+     A <= 2;
+  end generate;
+  gen3 : if in_vec'length > 2 generate
+     A <= 3;
+  end generate;
+end architecture;
diff --git a/testsuite/gna/issue151/testsuite.sh b/testsuite/gna/issue151/testsuite.sh
new file mode 100755
index 000000000..a77ea351b
--- /dev/null
+++ b/testsuite/gna/issue151/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze tb.vhdl
+clean
+
+echo "Test successful"
-- 
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