From 3f4ad3263f7e5294e20166c1396db48826a4bda5 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 30 Oct 2017 05:45:23 +0100 Subject: Add testcase for previous commit. --- testsuite/gna/bug079/repro1.vhdl | 19 +++++++++++++++++++ testsuite/gna/bug079/repro2.vhdl | 25 +++++++++++++++++++++++++ testsuite/gna/bug079/testsuite.sh | 13 +++++++++++++ 3 files changed, 57 insertions(+) create mode 100644 testsuite/gna/bug079/repro1.vhdl create mode 100644 testsuite/gna/bug079/repro2.vhdl create mode 100755 testsuite/gna/bug079/testsuite.sh (limited to 'testsuite/gna/bug079') diff --git a/testsuite/gna/bug079/repro1.vhdl b/testsuite/gna/bug079/repro1.vhdl new file mode 100644 index 000000000..08d122f1f --- /dev/null +++ b/testsuite/gna/bug079/repro1.vhdl @@ -0,0 +1,19 @@ +entity repro1 is +end repro1; + +architecture behav of repro1 is +begin + + process + variable var : natural; + + procedure proc (var : natural) is + begin + assert var = 5; + end; + begin + var := 5; + proc (var => var); + wait; + end process; +end behav; diff --git a/testsuite/gna/bug079/repro2.vhdl b/testsuite/gna/bug079/repro2.vhdl new file mode 100644 index 000000000..d1cec45bb --- /dev/null +++ b/testsuite/gna/bug079/repro2.vhdl @@ -0,0 +1,25 @@ +entity repro2 is +end repro2; + +architecture behav of repro2 is +begin + + process + type my_rec is record + inc : natural; + b : bit; + end record; + + constant bv : bit_vector := x"45"; + + procedure proc (v : my_rec; bv : bit) is + begin + assert v.b = bv; + end; + begin + proc (v => (inc => 3, + b => bv(3)), + bv => '0'); + wait; + end process; +end behav; diff --git a/testsuite/gna/bug079/testsuite.sh b/testsuite/gna/bug079/testsuite.sh new file mode 100755 index 000000000..e9441fcef --- /dev/null +++ b/testsuite/gna/bug079/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze repro1.vhdl +elab_simulate repro1 + +analyze repro2.vhdl +elab_simulate repro2 + +clean + +echo "Test successful" -- cgit v1.2.3